公开(公告)号：USRE37435E1

公开(公告)日：2001-11-06

申请号：US08810977

申请日：1997-02-27

Applicant: Shuji Yoshimura ,  Satoshi Kakuma ,  Naoki Aihara ,  Yasuhiro Aso ,  Masami Murayama

Inventor： Shuji Yoshimura ,  Satoshi Kakuma ,  Naoki Aihara ,  Yasuhiro Aso ,  Masami Murayama

IPC: H04J314

CPC classification number: H04L12/5602 ,  H04L49/3081 ,  H04L2012/5636 ,  H04L2012/5651 ,  H04L2012/5652

Abstract: A supervision control system for an ATM cell switching system counts the number of cells transmitted from a subscriber in a predetermined duration unit, attaches a sign to the cells when the counted value exceeds a predetermined value, and discards the cells to which the sign is attached when a buffer does not have enough capacity during a cell multiplexation.

Abstract translation: 用于ATM信元交换系统的监控控制系统以预定持续时间为单位对从用户发送的小区数进行计数，当计数值超过预定值时，向小区附加符号，并丢弃符号附加到的小区 当缓冲器在单元复用期间没有足够的容量时。

公开(公告)号：US5532682A

公开(公告)日：1996-07-02

申请号：US110209

申请日：1993-08-23

Applicant: Masami Murayama ,  Shuji Yoshimura ,  Tetsuo Kawamata ,  Atsushi Yoshioka

Inventor： Masami Murayama ,  Shuji Yoshimura ,  Tetsuo Kawamata ,  Atsushi Yoshioka

IPC: H04Q3/545 ,  G05B23/02 ,  G06F13/40 ,  H04L12/00

CPC classification number: G06F13/4018

Abstract: A control data transmission system controls an electronic switching system with few signal lines. Control data are split into a plurality of fixed-length bit blocks. The control data sequence number specification signals identify the fixed-length bit blocks. The control data sequence number specification signals are paired with corresponding control data signals carrying the contents of one of the fixed-length bit blocks and a control data validity specification signal for validating transmission of the control data. The control data sequence number specification signals are decoded and the contents of respective bit blocks carried by the control data signals are stored according to the decoding result and the control data validity specification signal. When the contents of the fixed-length bit blocks carried by the control data signals for one unit of control data are stored, the control data are analyzed.

Abstract translation: 控制数据传输系统控制具有很少信号线的电子交换系统。 控制数据被分割成多个固定长度位块。 控制数据序列号规范信号识别固定长度位块。 控制数据序列号指定信号与携带固定长度位块之一的内容的对应控制数据信号和用于验证控制数据传输的控制数据有效性指定信号配对。 对控制数据序列号指定信号进行解码，并且根据解码结果和控制数据有效性指定信号来存储由控制数据信号承载的各个位块的内容。 当存储由一个控制数据的控制数据信号承载的固定长度位块的内容时，分析控制数据。

公开(公告)号：US5504742A

公开(公告)日：1996-04-02

申请号：US139589

申请日：1993-10-20

Applicant: Satoshi Kakuma ,  Shuji Yoshimura ,  Shiro Uriu ,  Naoki Fukuda

Inventor： Satoshi Kakuma ,  Shuji Yoshimura ,  Shiro Uriu ,  Naoki Fukuda

IPC: H04J3/00 ,  H04J3/24 ,  H04L12/70 ,  H04L12/891 ,  H04L12/951 ,  H04Q11/04 ,  H04J3/12

CPC classification number: H04L49/3081 ,  H04J3/247 ,  H04L49/30 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5615 ,  H04L2012/5672

Abstract: A broadband ISDN remote multiplexer, which is constructed by separating a subscriber line interfacing section from an ATM exchange and installing the same at a remote location connected via a high-speed transmission line, comprises: a first interface unit for carrying out conversion between a transmitted signal of UNI format, carrying a destination number in its GFC field and transmitted over a transmission medium interconnecting the ATM exchange and the broadband ISDN remote multiplexer, and a first path-control signal that directs a connection within the remote multiplexer in accordance with the destination number; a plurality of subscriber line interface units for terminating respectively the plurality of broadband ISDN subscriber lines; and a multiplexing/demultiplexing unit for making a connection between the first interface unit and each of the subscriber line interface units in accordance with the first path-control signal.

Abstract translation: 宽带ISDN远程多路复用器，其通过将用户线接口部分与ATM交换机分离并将其安装在经由高速传输线路连接的远程位置而构成，包括：第一接口单元，用于在发送的 UNI格式的信号，在其GFC字段中携带目的地号码并通过互连ATM交换机和宽带ISDN远程多路复用器的传输介质传送，以及第一路径控制信号，其根据目的地引导远程多路复用器内的连接 数; 多个用户线接口单元，分别用于终止多个宽带ISDN用户线; 以及复用/解复用单元，用于根据第一路径控制信号在第一接口单元和每个用户线路接口单元之间进行连接。

公开(公告)号：US5361251A

公开(公告)日：1994-11-01

申请号：US854476

申请日：1992-03-17

Applicant: Naoki Aihara ,  Shuji Yoshimura ,  Naoki Fukuda ,  Tadashi Hoshino

Inventor： Naoki Aihara ,  Shuji Yoshimura ,  Naoki Fukuda ,  Tadashi Hoshino

IPC: H04L12/70 ,  H04L12/813 ,  H04L12/56

CPC classification number: H04L12/5602 ,  H04L2012/5636

Abstract: It is determined whether or not a passing cell is a cell to be measured. If yes, a signal synchronous with the passing cycle of the cell is generated by a synchronous signal generator. The synchronous signal is digitally processed by a digital signal processor. Thus, each parameter related to the number of passing cells is obtained by converting the analysis based on the time axis to the area analysis based on the frequency axis.

Abstract translation: 确定通过的细胞是否是要测量的细胞。 如果是，则由同步信号发生器产生与小区的通过周期同步的信号。 同步信号由数字信号处理器进行数字处理。 因此，通过将基于时间轴的分析转换为基于频率轴的区域分析来获得与通过的细胞数相关的每个参数。

公开(公告)号：US5251204A

公开(公告)日：1993-10-05

申请号：US762338

申请日：1991-09-19

Applicant: Naoyuki Izawa ,  Shuji Yoshimura ,  Satoshi Kakuma

Inventor： Naoyuki Izawa ,  Shuji Yoshimura ,  Satoshi Kakuma

IPC: H04J3/14 ,  H04J3/16 ,  H04L12/70 ,  H04Q11/04

CPC classification number: H04Q11/0478 ,  H04J3/14 ,  H04J3/1617 ,  H04J2203/0089 ,  H04L2012/5628 ,  H04L2012/5672

Abstract: The present invention relates to a transmission line test method in the broadband ISDN for assembling an ATM formatted cell into a frame and sending it in the synchronous optical network (SONET) formatted transmission line as a protocol of an optical fiber communication network. First, test data are inserted into an ATM cell according to a command of the central controlling unit in an ATM switching unit. Then, the test cell is sent through an ATM switch in the ATM switching unit after the insertion of the test data; the test data are extracted from the test cell turned around by an ATM layer provided between the ATM switch and the SONET-formatted transmission line or by a subscriber terminal adapter, or from the test frame (including the test cell) turned around by a terminator in the SONET-formatted transmission line or by a network terminator at a subscriber terminal in the transmission line; and finally a transmission test is conducted by checking the data in the line up to each turnaround point.

Abstract translation: 本发明涉及宽带ISDN中用于将ATM格式化小区组装成帧并在作为光纤通信网络的协议的同步光网络（SONET）格式化传输线路中发送它的传输线路测试方法。 首先，根据ATM交换单元中的中央控制单元的命令将测试数据插入到ATM信元中。 然后，测试单元在插入测试数据之后通过ATM交换单元中的ATM交换机发送; 从由ATM交换机和SONET格式的传输线之间提供的ATM层或由用户终端适配器或由终端器转过的测试框（包括测试单元）转移的测试单元提取测试数据 在SONET格式的传输线路中，或者由传输线路中的用户终端的网络终端器; 最后通过检查直到每个周转点的行中的数据进行传输测试。

公开(公告)号：US5875177A

公开(公告)日：1999-02-23

申请号：US957387

申请日：1997-10-23

Applicant: Shiro Uriu ,  Yoshihiro Uchida ,  Shuji Yoshimura

Inventor： Shiro Uriu ,  Yoshihiro Uchida ,  Shuji Yoshimura

IPC: H04J3/14 ,  H04L12/26 ,  H04L12/28 ,  H04L12/70 ,  H04Q11/04

CPC classification number: H04J3/14 ,  H04Q11/0478 ,  H04L2012/5628

Abstract: A sending trunk on the input side of an ATM switch is equipped with a test cell generating section, and a receiving trunk on the output side of the ATM switch is equipped with a test cell detecting section. The test cell generating section includes a unit for setting a test cell identifier in the header of a test cell and a unit for generating pieces of data with regularity in the information field of the test cell. The test cell detecting section includes a unit for detecting the test cell identifier from the header of a cell received and a unit for detecting regularity from data in the information field of the cell received. When a test cell is transmitted, the test cell detecting section evaluates the result of a test on the basis of the result of detection of the test cell identifier from the header of the test cell and the result of detection of the regularity from data in the information field of the test cell.

Abstract translation: 在ATM交换机的输入侧的发送中继装置具有测试小区生成部分，ATM交换机的输出侧的接收中继装备有测试小区检测部分。 测试小区生成部分包括用于在测试小区的头部中设置测试小区标识符的单元和用于在测试小区的信息字段中规则地生成数据片段的单元。 测试小区检测部分包括从接收的小区的头部检测测试小区标识符的单元和用于从所接收的小区的信息字段中的数据检测规则性的单元。 当测试单元被发送时，测试单元检测部分根据测试单元标识符的检测结果和来自测试单元的标题的规则性的检测结果来评估测试结果 测试单元的信息字段。

公开(公告)号：US5345451A

公开(公告)日：1994-09-06

申请号：US848170

申请日：1992-03-10

Applicant: Shiro Uriu ,  Shuji Yoshimura

Inventor： Shiro Uriu ,  Shuji Yoshimura

IPC: H04L7/00 ,  H03M13/00 ,  H04L1/00 ,  H04L7/04 ,  H04L12/70 ,  H04Q11/04 ,  G06F11/10

CPC classification number: H04L1/0061 ,  H04L1/0052 ,  H04L1/0072 ,  H04L7/048 ,  H04Q11/0478 ,  H04L2012/5673 ,  H04L2012/5674

Abstract: A CRC operating unit which performs a CRC operation on received data using as an initial value a CRC operation result actual value obtained in a previous operation, and outputs a CRC operation result actual value. A delay unit delays the CRC operation result actual value by the time taken for a header part to be entered. The CRC operation result derivation unit outputs as a CRC operation result derivation value an operation result obtained by a CRC operation performed for all the receiving data of a header part provided with the above described CRC code using the CRC operation result actual value as an initial value. The coincidence detecting unit compares the CRC operation result actual value with the CRC operation result derivation value to detect the input timing of a header part as coincident timing for both values.

Abstract translation: CRC操作单元，其使用在先前操作中获得的CRC运算结果实际值作为初始值对接收到的数据执行CRC操作，并输出CRC运算结果实际值。 延迟单元将CRC运算结果实际值延迟到输入标题部分所花费的时间。 CRC运算结果导出部将CRC运算结果导出值作为初始值输出作为CRC运算结果导出值的运算结果，该运算结果通过对具有上述CRC码的头部部分的所有接收数据执行的CRC运算获得， 。 一致检测单元将CRC运算结果实际值与CRC运算结果推导值进行比较，以检测报头部分的输入定时为两个值的重合定时。

公开(公告)号：US5271010A

公开(公告)日：1993-12-14

申请号：US780108

申请日：1991-10-21

Applicant: Hiroshi Miyake ,  Satoshi Kakuma ,  Shuji Yoshimura ,  Naoki Aihara ,  Naoki Fukuda

Inventor： Hiroshi Miyake ,  Satoshi Kakuma ,  Shuji Yoshimura ,  Naoki Aihara ,  Naoki Fukuda

IPC: H04L12/947 ,  H04J3/24

CPC classification number: H04L49/309 ,  H04L49/3009 ,  H04L49/3081

Abstract: A virtual channel converter converts a virtual path identifier and a virtual channel identifier, e.g. in a twenty-eight (28) bit frame, attached to the header part of an incoming ATM cell on an input highway to an ATM switcher to identifiers to be attached to an outgoing ATM cell on an output highway capable of fully supporting all the combinations, two hundred fifty-six (256) for example, of a virtual path identifier and a virtual channel identifier no matter where the virtual path identifier and the virtual channel identifier are located in the twenty-eight (28) bit frame. The virtual channel converter comprises a plurality of identifier comparator units and a controller. Each of the identifier comparator units has an input identifier memory for storing an identifier attached to an ATM cell and a comparator for comparing the identifiers of an incoming ATM cell with the identifiers stored in the input identifier memory. The controller instructs respective input identifier memories to store all the values of identifiers attached to incoming ATM cells from a user to a switcher on a one-to-one basis.

公开(公告)号：US5691977A

公开(公告)日：1997-11-25

申请号：US580534

申请日：1995-12-29

Applicant: Shuji Yoshimura ,  Satoshi Kakuma ,  Masami Murayama ,  Shiro Uriu ,  Tadashi Hoshino

Inventor： Shuji Yoshimura ,  Satoshi Kakuma ,  Masami Murayama ,  Shiro Uriu ,  Tadashi Hoshino

IPC: H04M3/00 ,  H04L12/28 ,  H04L12/70 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/56

CPC classification number: H04Q11/0478 ,  H04L49/3081 ,  H04L2012/5614 ,  H04L2012/5619

Abstract: In a data access device for writing into or read from a data conversion table on the basis of a clock signal extracted from a cell being transferred over a line, a clock signal generator of the invention generates a second clock signal which differs from the first clock signal extracted from an incoming cell. A write/read control unit writes data into or reads data for maintenance from the data conversion table on the basis of either the first clock signal or the second clock signal when the line is normal. In the event of the occurrence of a failure in the line, on the other hand, the write/read control circuit permits the data conversion table to be written into or read from for maintenance on the basis of the second clock signal.

Abstract translation: 本发明的时钟信号发生器根据从通过线路传输的单元提取的时钟信号写入数据转换表或从数据转换表读取数据存取装置，产生与第一时钟不同的第二时钟信号 从进入的小区提取的信号。 写入/读取控制单元在线路正常时，基于第一时钟信号或第二时钟信号，将数据写入数据转换表或从数据转换表读取数据进行维护。 另一方面，在线路中出现故障的情况下，写入/读取控制电路允许数据转换表基于第二时钟信号写入或读取以进行维护。

公开(公告)号：US5602826A

公开(公告)日：1997-02-11

申请号：US565048

申请日：1995-11-30

Applicant: Shuji Yoshimura ,  Shiro Uriu ,  Satoshi Kakuma

Inventor： Shuji Yoshimura ,  Shiro Uriu ,  Satoshi Kakuma

IPC: H04L12/56 ,  H04Q11/04 ,  H04J3/14

CPC classification number: H04Q11/0478 ,  H04L2012/5628 ,  H04L2012/5652

Abstract: A test system exactly checks the integrity of data in an ATM system, and generates a test cell of a desired band. In the first aspect of the system in which data stored in an ATM cell are transmitted in an 8-bit parallel format in the ATM system, a test cell generating device connected to an input line outputs a test cell having 1 in all of the eight bits or having zero in all of the eight bits, and the test cell confirming device connected to an output line of the ATM switch detects the above described data. In the second aspect, the test cell generating device provided in an input trunk outputs a test cell of a desired band based on a ratio between two optional integers N and n (N.gtoreq.n), the state of a buffer of the ATM switch is monitored, and a load test is conducted to determine whether or not any cell has been destroyed.

Abstract translation: 测试系统精确地检查ATM系统中数据的完整性，并生成所需频段的测试单元。 在ATM系统中以8比特并行格式发送存储在ATM信元中的数据的系统的第一方面中，连接到输入线的测试单元生成装置输出具有1个全部八个的测试单元 位或在所有八位中具有零，并且连接到ATM交换机的输出线的测试单元确认装置检测上述数据。 在第二方面，提供在输入中继线中的测试单元产生装置基于两个可选整数N和n（N> / = n）之间的比率输出所需频带的测试单元，ATM的缓冲器的状态 监控开关，并进行负载测试，以确定任何电池是否已被破坏。