发明授权
- 专利标题： Weighted summing circuit
- 专利标题（中）： 加权求和电路
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申请号： US190926申请日： 1994-02-03
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公开(公告)号： US5465064A公开(公告)日： 1995-11-07
- 发明人: Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
- 申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
- 申请人地址： JPX Tokyo JPX Tokyo
- 专利权人： Yozan Inc.,Sharp Corporation
- 当前专利权人： Yozan Inc.,Sharp Corporation
- 当前专利权人地址： JPX Tokyo JPX Tokyo
- 优先权： JPX5-040424 19930204
- 主分类号： G06G7/14
- IPC分类号： G06G7/14 ; H03K12/00
摘要：
A weighted summing circuit for minimizing bias voltage influence includes capacitive coupling and a closed loop inverter. The weighted summing circuit inputs the output of a capacitive coupling CP.sub.1 to serially connected first and second inverters INV.sub.1 and INV.sub.2, and includes grounded weighted capacitances C.sub.32 and C.sub.11, capacitance C.sub.21 connecting the first and the second inverters INV.sub.1 and INV.sub.2, and a capacitive coupling CP.sub.1 such that the closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are substantially equal. The closed loop gains of the first and second inverters INV.sub.1 and INV.sub.2 are balanced.