Invention Grant
- Patent Title: Multilayer wiring board fabricating method
- Patent Title (中): 多层布线板制造方法
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Application No.: US113983Application Date: 1993-08-30
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Publication No.: US5480048APublication Date: 1996-01-02
- Inventor: Naoya Kitamura , Hisashi Sugiyama , Yoshihide Yamaguchi , Masayuki Kyoui , Hideyasu Murooka , Ryoji Iwamura , Makio Watanabe
- Applicant: Naoya Kitamura , Hisashi Sugiyama , Yoshihide Yamaguchi , Masayuki Kyoui , Hideyasu Murooka , Ryoji Iwamura , Makio Watanabe
- Applicant Address: JPX Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JPX Tokyo
- Priority: JPX4-236612 19920904
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H05K3/10 ; H05K3/24 ; H05K3/42 ; H05K3/46 ; B44C1/22 ; B29C37/00
Abstract:
A multilayer wiring board fabricating method and a multilayer wiring board fabricated with use of the method that a solvent-free fluid polymer precursor is put on a wiring layer of a base substrate, and space among the wirings is exhausted and is filled with the precursor, and the precursor is hardened under a hydrostatic pressure and then the next wiring layer is formed before the above process is repeated one or more times. The multilayer wiring board fabricating method is excellent in the mass productivity and low cost and in that the wiring can be made highly dense with the substrate having vertical via conductors for connection among the conductor layers.
Public/Granted literature
- USD430976S Roman arch chair Public/Granted day:2000-09-19
Information query
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