发明授权
- 专利标题： Variable delay circuit
- 专利标题（中）： 可变延迟电路
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申请号： US394249申请日： 1995-02-24
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公开(公告)号： US5495197A公开(公告)日： 1996-02-27
- 发明人: Yokichi Hayashi , Hiroshi Tsukahara , Katsumi Ochiai , Masuhiro Yamada , Naoyoshi Watanabe
- 申请人： Yokichi Hayashi , Hiroshi Tsukahara , Katsumi Ochiai , Masuhiro Yamada , Naoyoshi Watanabe
- 申请人地址： JPX
- 专利权人： Advantest Corporation
- 当前专利权人： Advantest Corporation
- 当前专利权人地址： JPX
- 优先权： JPX3-204365 19910814; JPX3-293230 19911108; JPX3-293231 19911108; JPX3-293232 19911108; JPX3-293233 19911108; JPX3-98755U 19911129
- 主分类号： H03K5/13
- IPC分类号： H03K5/13 ; H03K17/16 ; H03H11/26
摘要：
First and second exclusive-OR gates (hereinafter referred to as EXOR gates) are provided, which are both connected at one input side to a delay input terminal. The other input side of the first EXOR gate is grounded and the other input side of the second EXOR gate is connected to a select signal input terminal. A capacitor is connected between the output side of the first EXOR gate and the output side of the second EXOR gate. The output side of the first EXOR gate is connected to a delay output terminal by way of a buffer which outputs logical levels. The buffer has a threshold value and outputs one or the other binary logical level depending on whether the input thereto is above or below a threshold value.
公开/授权文献
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