发明授权
- 专利标题： Process for forming multilayer wiring
- 专利标题（中）： 多层布线形成工艺
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申请号： US87027申请日： 1993-07-06
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公开(公告)号： US5498768A公开(公告)日： 1996-03-12
- 发明人: Eisuke Nishitani , Susumu Tsuzuku , Shigeru Kobayashi , Osamu Kasahara , Hiroki Nezu , Masakazu Ishino , Tsuyoshi Tamaru
- 申请人： Eisuke Nishitani , Susumu Tsuzuku , Shigeru Kobayashi , Osamu Kasahara , Hiroki Nezu , Masakazu Ishino , Tsuyoshi Tamaru
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX63-185598 19880727
- 主分类号： C23C16/02
- IPC分类号： C23C16/02 ; C23C16/04 ; C23C16/06 ; C23C16/54 ; H01L21/28 ; H01L21/285 ; H01L21/302 ; H01L21/3065 ; H01L21/31 ; H01L21/768 ; H01L23/522 ; H01L21/441
摘要：
The present invention relates to a method for filling small via holes provided to insulating film on a wafer to expose parts of the underlayer of the wafer by metal by means of CVD, and an apparatus therefor. The gist of the present invention lies in that, before CVD is conducted, a surface cleaning treatment of small via hole bottom underlayer surface and a stabilization treatment of insulating film surface activated thereby are carried out successively or simultaneously and optionally an anti-corrosive treatment is applied to underlayer surface, and then the CVD treatment is conducted without exposing the underlayer metal subjected to above treatments to the air. The present invention provides an effect of enabling via filling by metal which shows good selectivity and gives a low interfacial resistance between underlayer metal and filled metal.
公开/授权文献
- USD417133S Coupler lock for pintle drawbar eye 公开/授权日：1999-11-30