Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus

发明授权

US5513377A Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus 失效

标题翻译：输入输出元件具有使用接收的时钟信号的自定时接口，以对从并行总线接收的单独的相位对准位

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专利标题： Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus
专利标题（中）： 输入输出元件具有使用接收的时钟信号的自定时接口，以对从并行总线接收的单独的相位对准位
申请号： US261561

申请日： 1994-06-17
公开(公告)号： US5513377A

公开(公告)日： 1996-04-30
发明人: Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
申请人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
申请人地址： NY Armonk
专利权人： International Business Machines Corporation
当前专利权人： International Business Machines Corporation
当前专利权人地址： NY Armonk
主分类号： H04L29/00
IPC分类号： H04L29/00 ; G06F13/42 ; H04L7/00 ; G06F13/00

Input-output element has self timed interface using a received clock
signal to individually phase aligned bits received from a parallel bus

摘要：

An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.

摘要（中）：

增强的输入 - 输出元件具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准，以提供经济有效的模块化宽带输入/输出元件，可以经济地服务于两个通道，并可模块化地扩展以提供数百个通道。

公开/授权文献

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