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    Method and apparatus for performing control unit level recovery operations
    2.
    发明授权
    Method and apparatus for performing control unit level recovery operations 失效
    执行控制单元级别恢复操作的方法和装置

    公开(公告)号：US5423026A

    公开(公告)日：1995-06-06

    申请号：US755200

    申请日：1991-09-05

    申请人： Thomas E. Cook ,  Marten J. Halma ,  Allan S. Meritt ,  Harry M. Yudenfriend

    发明人： Thomas E. Cook ,  Marten J. Halma ,  Allan S. Meritt ,  Harry M. Yudenfriend

    IPC分类号： G06F11/14 ,  G06F11/00

    CPC分类号： G06F11/142

    摘要： Control unit level reset operations in systems having switched point-to-point I/O interface topologies is accomplished by determining and storing channel path identification numbers (CHPID's) and control unit link addresses (CULA's) for each device in the system, scanning this stored data to find devices whose CHPID's and CULA's match the CHPID and CULA for a device or a control unit having a reported error, quiescing devices with such matching CHPID's and CULA's, issuing a control unit level reset command and reactivating the quiesced devices. For systems having both multidropped and switched point-to-point topologies, provision is made for preliminarily determining whether a given control unit reset can be performed on the control unit level.

    摘要翻译： 通过确定和存储系统中每个设备的通道路径标识号（CHPID）和控制单元链路地址（CULA）来实现具有交换点对点I / O接口拓扑的系统中的控制单元电平复位操作，扫描该存储 数据以查找具有报告错误的设备或具有报告错误的控制单元的CHPID和CULA与CHPID和CULA匹配的设备，停止具有这种匹配的CHPID和CULA的设备，发出控制单元级别复位命令并重新激活静默设备。 对于具有多点和交换点对点拓扑的系统，提供预先确定是否可以在控制单元级别执行给定的控制单元复位。

    Input/output control system with plural channel paths to I/O devices
    6.
    发明授权
    Input/output control system with plural channel paths to I/O devices 失效
    I / O控制系统，用于基于其状态和其相关联的信道队列的可用时隙选择性地将工作分配给可用信道。

    公开(公告)号：US5548791A

    公开(公告)日：1996-08-20

    申请号：US279581

    申请日：1994-07-25

    申请人： Daniel F. Casper ,  Steven G. Glassen ,  Marten J. Halma ,  Sandra K. Ryan

    发明人： Daniel F. Casper ,  Steven G. Glassen ,  Marten J. Halma ,  Sandra K. Ryan

    IPC分类号： G06F13/12 ,  G06F13/14

    CPC分类号： G06F13/122

    摘要： A data processing system includes a host processor and host memory means. The processor interacts with a plurality of peripheral units through an I/O system that includes a plurality of channels, one or more I/O processors (IOP's), and control data in a system area of the host memory means. Each channel has an associated busy bit in a vector, and is provided with a one position queue for dispatching work to the channel. Each queue has a bit in a vector indicating its full or empty status. A very efficient algorithm for the assignment of work for peripherals by the IOP's is provided in a system that provides for multiple paths through multiple channels between the host and a particular peripheral using the busy vector and queue vector.

    摘要翻译： 数据处理系统包括主机处理器和主机存储器装置。 处理器通过包括多个信道，一个或多个I / O处理器（IOP）的I / O系统和主机存储器装置的系统区域中的控制数据与多个外围设备进行交互。 每个通道在向量中都有一个相关联的忙位，并且具有一个位置队列，用于将工作调度到通道。 每个队列都有一个向量中的位，表示其全部或空的状态。 在通过忙向量和队列向量提供主机与特定外设之间的多个通道的多个路径的系统中提供了用于由IOP为外围设备分配工作的非常有效的算法。