- 专利标题: Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory
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申请号: US260922申请日: 1994-06-15
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公开(公告)号: US5515334A公开(公告)日: 1996-05-07
- 发明人: Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
- 申请人: Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JPX Osaka
- 优先权: JPX5-145938 19930617; JPX5-258070 19930115
- 主分类号: G11C5/02
- IPC分类号: G11C5/02 ; G11C7/10 ; G11C11/4096 ; G11C7/00
摘要:
In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
公开/授权文献
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