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    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07280406B2

    公开(公告)日：2007-10-09

    申请号：US11344199

    申请日：2006-02-01

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C16/06

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor memory apparatus
    4.
    发明申请
    Semiconductor memory apparatus 有权
    半导体存储装置

    公开(公告)号：US20050146969A1

    公开(公告)日：2005-07-07

    申请号：US11023663

    申请日：2004-12-29

    申请人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

    发明人： Yasuo Murakuki ,  Masahiko Sakagami ,  Shunichi Iwanari

    IPC分类号： G01R31/28 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C17/18 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C17/18 ,  G11C29/785

    摘要： A semiconductor memory apparatus is provided which has a simple circuit configuration and is capable of randomly accessing fuse data. In the semiconductor memory apparatus of the present invention, a fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. In the semiconductor memory apparatus of the present invention, by allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.

    摘要翻译： 提供一种半导体存储装置，其具有简单的电路配置并且能够随机访问熔丝数据。 在本发明的半导体存储装置中，包括熔丝31的熔丝单元30连接到存储电路的一对位线。 熔丝31和熔丝数据输出电路（其包括电阻32和反相器33）通过熔丝选择开关34连接到存储电路的一对位线BLT和BLB。 在本发明的半导体存储装置中，通过允许用于选择存储单元的一对位线的列解码器12也用作用于选择熔丝的解码器电路，存储电路的位线可以用作 用于输出熔丝数据的信号线，由此减小电路尺寸并减小电路面积。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5841727A

    公开(公告)日：1998-11-24

    申请号：US867855

    申请日：1997-06-03

    申请人： Shunichi Iwanari ,  Hirohito Kikukawa

    发明人： Shunichi Iwanari ,  Hirohito Kikukawa

    IPC分类号： G11C11/408 ,  G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C11/406

    摘要： To restrain an increase in power consumption and a reduction in access speed, the following structure is adopted: An address is input to a row address input circuit and in correspondence with a row address output from the row address input circuit, a predecode signal is output from a row predecode circuit. An address is input to a block-select-signal generating circuit from which first and second block select signals are output for selecting either one of the first and second memory cell array blocks. First and second predecode-signal hold circuits provided in correspondence with the first and second memory cell array blocks hold predecode signals. First and second predecode signals held by the first and second predecode signal hold circuits are supplied to first and second row decode circuits, respectively, and the first and second predecode-signal hold circuits corresponding to the first and second block select signals update the contents being held.

    摘要翻译： 为了抑制功耗的增加和存取速度的降低，采用以下结构：将地址输入到行地址输入电路，并且与从行地址输入电路输出的行地址对应地输出预解码信号 来自一行预先解码电路。 地址被输入到块选择信号发生电路，从其输出第一和第二块选择信号以选择第一和第二存储单元阵列块中的任一个。 与第一和第二存储单元阵列块对应地设置的第一和第二预解码信号保持电路保持预解码信号。 由第一和第二预解码信号保持电路保持的第一和第二预解码信号分别被提供给第一和第二行解码电路，并且对应于第一和第二块选择信号的第一和第二预解码信号保持电路更新内容为 保持。

    Semiconductor integrated circuit with a data transmission circuit
    7.
    发明授权
    Semiconductor integrated circuit with a data transmission circuit 失效
    具有数据传输电路的半导体集成电路

    公开(公告)号：US5642323A

    公开(公告)日：1997-06-24

    申请号：US573076

    申请日：1995-12-15

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Ichiro Nakao ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

    摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

    Semiconductor memory device having a prolonged data holding time
    8.
    发明授权
    Semiconductor memory device having a prolonged data holding time 失效
    半导体存储器件具有延长的数据保持时间

    公开(公告)号：US5426601A

    公开(公告)日：1995-06-20

    申请号：US184933

    申请日：1994-01-24

    申请人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    发明人： Masashi Agata ,  Hironori Akamatsu ,  Hirohito Kikukawa ,  Akihiro Sawada ,  Shunichi Iwanari

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C5/143

    摘要： An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell. This adequately prolongs the data-holding time with no sacrifice in memory cell voltage resistance.

    摘要翻译： 外部电源电压VCC作为第一内部电源电压VPERI施加到外围电路。 如果VCC在VCC推荐工作条件下规定的电压范围内VCC不大于下限电压V0L，则电源电压控制电路输出高逻辑电平的电压控制信号VSIG，否则输出低逻辑电平的VSIG。 电源电路将第二内部电源电压VW和第三内部电源电压VWORD施加到存储单元部分。 如果VSIG为高电平，则VW等于VPERI，而另一方面，VW是VPERI升压的电压。 VWORD是由于将VW进一步升高而产生的电压。 行解码器将VW发送到一行读出放大器的使能信号线上，并将VWORD发送到存储单元阵列的字线上，以使VW成为存储单元的高逻辑电平数据写入电压。 这样就可以在不牺牲存储单元耐压的情况下充分延长数据保持时间。

    Semiconductor memory device and semiconductor integrated circuit
    9.
    发明授权
    Semiconductor memory device and semiconductor integrated circuit 有权
    半导体存储器件和半导体集成电路

    公开(公告)号：US08422267B2

    公开(公告)日：2013-04-16

    申请号：US13243312

    申请日：2011-09-23

    申请人： Shunichi Iwanari ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Yasuo Murakuki

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C7/08 ,  G11C8/08

    摘要： A semiconductor memory device includes a plurality of memory cells connected to a common bit line, a plurality of select lines each configured to select at least one of the memory cells, a plurality of drive circuits each configured to drive at least one of the select lines, a sense amplifier configured to amplify a voltage occurring at the bit line depending on data stored in the selected memory cell. A memory region where the memory cells are provided has a first region and a second region. When the first region is read, a larger number of the select lines are simultaneously driven by the corresponding common drive circuit than those in the second region, and a larger number of the memory cells are simultaneously selected than those in the second region.

    摘要翻译： 半导体存储器件包括连接到公共位线的多个存储器单元，多个选择线，每个选择线被配置为选择至少一个存储器单元，多个驱动电路，每个驱动电路被配置为驱动选择线中的至少一个 ，读出放大器，被配置为根据存储在所选择的存储单元中的数据放大在位线处发生的电压。 提供有存储单元的存储区域具有第一区域和第二区域。 当读取第一区域时，相应的公共驱动电路与第二区域同时驱动较大数量的选择线，并且与第二区域同时选择更多数量的存储器单元。

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体存储器件和半导体集成电路

    公开(公告)号：US20120075905A1

    公开(公告)日：2012-03-29

    申请号：US13243312

    申请日：2011-09-23

    申请人： Shunichi IWANARI ,  Yasuo Murakaki

    发明人： Shunichi IWANARI ,  Yasuo Murakaki

    IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C7/06

    CPC分类号： G11C11/22 ,  G11C7/08 ,  G11C8/08

    摘要： A semiconductor memory device includes a plurality of memory cells connected to a common bit line, a plurality of select lines each configured to select at least one of the memory cells, a plurality of drive circuits each configured to drive at least one of the select lines, a sense amplifier configured to amplify a voltage occurring at the bit line depending on data stored in the selected memory cell. A memory region where the memory cells are provided has a first region and a second region. When the first region is read, a larger number of the select lines are simultaneously driven by the corresponding common drive circuit than those in the second region, and a larger number of the memory cells are simultaneously selected than those in the second region.

    摘要翻译： 半导体存储器件包括连接到公共位线的多个存储器单元，多个选择线，每个选择线被配置为选择至少一个存储器单元，多个驱动电路，每个驱动电路被配置为驱动选择线中的至少一个 ，读出放大器，被配置为根据存储在所选择的存储单元中的数据放大在位线处发生的电压。 提供有存储单元的存储区域具有第一区域和第二区域。 当读取第一区域时，相应的公共驱动电路与第二区域同时驱动较大数量的选择线，并且与第二区域同时选择更多数量的存储器单元。