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公开(公告)号：US07193908B2
公开(公告)日：2007-03-20
申请号：US11202230
申请日：2005-08-12
IPC分类号： G11C7/00
摘要： Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.
摘要翻译： 提供一种半导体存储器，包括：电压转换电路，其对第一和第二电阻元件之间的电阻差进行电压转换; 电压比较电路，其输出与电压转换相对应的输出; 用于保持电压比较电路的输出的锁存电路; 以及切换并连接电压转换电路和电压比较电路的开关电路。
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公开(公告)号：US20060114708A1
公开(公告)日：2006-06-01
申请号：US11272818
申请日：2005-11-15
IPC分类号： G11C17/00
摘要： Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.
摘要翻译： 从解码器输出的选择信号根据单元组指定电路中的位单元中的状态（发生或不发生）或熔丝选择性地设置为高。 然后，晶体管栅极中的一个导通，从而选择写入/读出数据的数据位单元组。 因此，可以通过在单元组指定电路中顺序吹送保险丝来重写多个存储的数据。
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公开(公告)号：US07050347B2
公开(公告)日：2006-05-23
申请号：US11038025
申请日：2005-01-21
IPC分类号： G11C7/02
CPC分类号： G11C29/50 , G11C2029/1204 , G11C2029/5004
摘要： In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.
摘要翻译： 在正常操作中，输出用于放大第一和第二位单元之间的差分的差分放大器的输出作为读出数据。 在测试模式中，当第一控制信号被设置为“H”时，差分放大器的输出被固定为“H”，从而通过门读出第一位单元的输出。
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公开(公告)号：US20060039209A1
公开(公告)日：2006-02-23
申请号：US11202230
申请日：2005-08-12
IPC分类号： G11C7/00
摘要： Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.
摘要翻译： 提供一种半导体存储器，包括：电压转换电路，其对第一和第二电阻元件之间的电阻差进行电压转换; 电压比较电路，其输出与电压转换相对应的输出; 用于保持电压比较电路的输出的锁存电路; 以及切换并连接电压转换电路和电压比较电路的开关电路。
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公开(公告)号：US06961260B2
公开(公告)日：2005-11-01
申请号：US10802860
申请日：2004-03-18
申请人： Masanori Shirahama , Masashi Agata
发明人： Masanori Shirahama , Masashi Agata
IPC分类号： H01L27/10 , G11C5/02 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C5/06
CPC分类号： G11C5/025 , G11C11/4074 , G11C11/4085
摘要： The layout of the semiconductor storage circuit is generated by placing, along a word line direction, a desired number of a circuit extension units each of which includes a data access circuit section, memory cell sub arrays and a power circuit section arranged along a bit line direction. The data access circuit section is driven by a driver circuit provided in the data access circuit section, and the driving operation of the driver circuit is controlled by a driver circuit provided in a control circuit section. Also, a voltage supplying operation of the power circuit section is controlled by a driver circuit provided in a power control circuit section.
摘要翻译： 半导体存储电路的布局通过沿字线方向放置所需数量的电路扩展单元而产生，每个电路扩展单元包括数据访问电路部分，存储单元子阵列和沿着位线布置的电源电路部分 方向。 数据存取电路部分由设在数据存取电路部分的驱动电路驱动，驱动电路的驱动操作由设在控制电路部分的驱动电路控制。 此外，电力电路部分的电压供给操作由设置在功率控制电路部分中的驱动电路控制。
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公开(公告)号：US20050052926A1
公开(公告)日：2005-03-10
申请号：US10935278
申请日：2004-09-08
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0425
摘要： A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.
摘要翻译： 非易失性半导体存储器件包括：第一位单元，包括其源极和漏极连接以形成第一控制栅极的第一MOS晶体管和具有与第一MOS晶体管共同的浮动栅极的第二MOS晶体管; 第二位单元，包括其源极和漏极连接以形成第二控制栅极的第三MOS晶体管和具有与第三MOS晶体管共同的浮置栅极的第四MOS晶体管; 以及差分放大器，其从相应的第二和第四MOS晶体管的漏极接收输入信号。
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公开(公告)号：US06751116B2
公开(公告)日：2004-06-15
申请号：US10233486
申请日：2002-09-04
申请人： Naoki Kuroda , Masashi Agata
发明人： Naoki Kuroda , Masashi Agata
IPC分类号： G11C1124
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281
摘要： A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.
摘要翻译： 包括要访问的存储单元的第一晶体管，第一位线对，第一列选择开关和数据线对的路径的端口A与包括存储器单元的第二晶体管的路径的端口B交错 要被访问的第二位线对，第二列选择开关和数据线对在时钟的两个周期中。 读取放大器将从位线对传送的数据放大到数据线对，并在时钟的一个周期内将结果数据输出到输入/输出缓冲器。 输入/输出缓冲器在时钟的一个周期内将从读取放大器接收到的数据输出到外部。
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公开(公告)号：US06285723B1
公开(公告)日：2001-09-04
申请号：US09513714
申请日：2000-02-25
申请人： Toshio Yamada , Masashi Agata
发明人： Toshio Yamada , Masashi Agata
IPC分类号： H04L700
CPC分类号： G06F1/04 , G06F1/10 , H03K5/131 , H03K5/133 , H03K5/135 , H03K2005/00052 , H03K2005/00286
摘要： A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.
摘要翻译： 根据本发明的定时信号产生电路包括：延迟电路，用于在延迟时钟信号的同时传输输入时钟信号，延迟电路具有多个中间抽头，能够在延迟电路的相应位置输出时钟信号 ; 用于在延迟时钟信号的同时发送时钟信号的检测延迟电路，所述检测延迟电路具有能够在其检测延迟电路中的相应位置处输出时钟信号的多个中间抽头; 多个采样/保持电路，每个采样/保持电路均具有采样信号端子，采样信号端子连接到检测延迟电路的多个中间抽头中的相应的一个; 用于检测时钟信号的边沿的多个边界延迟电路，边界检测电路连接到取样/保持电路的各个输出端; 以及输出选择电路，用于经由根据由边界检测电路检测的时钟信号的边缘位置选择的多个中间抽头中的至少一个提取时钟信号，输出选择电路将提取的时钟信号作为定时输出 信号。
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9.发明授权公开(公告)号：US06229758B1
公开(公告)日：2001-05-08
申请号：US09662149
申请日：2000-09-14
申请人： Masashi Agata
发明人： Masashi Agata
IPC分类号： G11C800
CPC分类号： G11C7/1072
摘要： The semiconductor memory device of the invention includes: a data storage section for storing data thereon; a data write section for writing data on the storage section; and a data read section for reading out the data stored on the storage section. The read section generates a read clock signal responsive to an external clock signal, and the write section generates a write clock signal responsive to the external clock signal. And one cycle of the read clock signal is set shorter than one cycle of the write clock signal.
摘要翻译： 本发明的半导体存储器件包括：数据存储部分，用于在其上存储数据; 用于在存储部分上写入数据的数据写入部分; 以及用于读出存储在存储部分上的数据的数据读取部分。 读取部分响应于外部时钟信号产生读取时钟信号，并且写入部分响应于外部时钟信号产生写入时钟信号。 读时钟信号的一个周期被设置为短于写时钟信号的一个周期。
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公开(公告)号：US20060083046A1
公开(公告)日：2006-04-20
申请号：US11245075
申请日：2005-10-07
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.
摘要翻译： 熔丝器件和程序晶体管彼此串联连接。 触发器响应于启动信号而导通，程序晶体管开始保险丝装置的编程。 2输入NAND电路在熔断器件的电阻值的变化增加以达到预定值的时间点输出结束信号，同时通过接点处的电压变化来监测熔丝器件的电阻值的变化 保险丝装置和程序晶体管的点。 触发器关闭，响应于结束信号，程序晶体管自动终止保险丝装置的程序。 因此，保险丝装置的电阻值在最小程序时间内增加到预定电平。
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