发明授权
- 专利标题: Semiconductor memory device
- 专利标题(中): 半导体存储器件
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申请号: US364990申请日: 1994-12-28
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公开(公告)号: US5523980A公开(公告)日: 1996-06-04
- 发明人: Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
- 申请人: Koji Sakui , Hiroshi Nakamura , Tomoharu Tanaka , Masaki Momodomi , Fujio Masuoka , Kazunori Ohuchi , Tetsuo Endoh
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX5-354215 19931228; JPX6-198841 19940823
- 主分类号: G11C16/06
- IPC分类号: G11C16/06 ; G11C8/12 ; G11C16/02 ; G11C16/04 ; G11C29/00 ; G11C29/34 ; H01L29/78 ; G11C8/00
摘要:
A NAND-cell type EEPROM having a plurality of bit lines, a plurality of control gate lines intersecting with the bit lines, and a plurality of memory cells driven by applying a potential to the control gate lines for selectively storing data, supplying data to the bit lines and receiving data therefrom. The memory cells form a plurality of cell units. The memory cells constituting each cell unit are connected in series to one bit line by a common selecting gate transistor. A plurality of data latch circuits are provided on the bit lines, respectively, for storing data to be written into the memory cells selected by the control gate lines. Further, a plurality of selecting gate drivers are provided to correspond to the cell units, respectively, for driving the control gate lines. A row decoder decodes row addresses for driving the selecting gate drivers and the control gate lines. A plurality of block-address latch circuits are provided to correspond to the selecting gate drivers, respectively, for temporarily storing signals derived from a row address by the row decoder, thereby to select at least two of the selecting gate drivers at the same time in order to write data.
公开/授权文献
- USD321294S Toy chest 公开/授权日:1991-11-05
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