A memory cell structure for a semiconductor device includes a capacitor for storing electric charge, a first transistor for controlling storage and release of charge in the capacitor, and a second transistor interposed in a conduction path which connects the capacitor and the first transistor to each other. The second transistor serves as a cut-off transistor for interrupting the electrical connection between a charge storing capacitor and the first transistor when the capacitor is in the charged state, to thereby prevent effectively the charge from leaking by way of the source region of the first transistor. A dynamic semiconductor memory device includes a memory cell array having a plurality of memory cells of this.