发明授权
US5534723A Semiconductor integrated circuit device having output and internal
circuit MISFETS
失效
具有输出和内部电路MISFETS的半导体集成电路器件
- 专利标题: Semiconductor integrated circuit device having output and internal circuit MISFETS
- 专利标题(中): 具有输出和内部电路MISFETS的半导体集成电路器件
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申请号: US431568申请日: 1995-04-27
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公开(公告)号: US5534723A公开(公告)日: 1996-07-09
- 发明人: Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
- 申请人: Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX58-243801 19831226; JPX60-16508 19850201
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238 ; H01L21/8242 ; H01L27/02 ; H01L27/092 ; H01L29/78 ; H01L29/06
摘要:
Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
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