公开(公告)号：US5436483A

公开(公告)日：1995-07-25

申请号：US142965

申请日：1993-10-29

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US5610089A

公开(公告)日：1997-03-11

申请号：US429868

申请日：1995-04-27

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L27/10873 ,  H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L29/78 ,  H01L29/7836

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US5534723A

公开(公告)日：1996-07-09

申请号：US431568

申请日：1995-04-27

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US5436484A

公开(公告)日：1995-07-25

申请号：US143151

申请日：1993-10-29

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US5276346A

公开(公告)日：1994-01-04

申请号：US815863

申请日：1992-01-02

申请人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

发明人： Hidetoshi Iwai ,  Kazumichi Mitsusada ,  Masamichi Ishihara ,  Tetsuro Matsumoto ,  Kazuyuki Miyazawa ,  Hisao Katto ,  Kousuke Okuyama

IPC分类号： H01L21/8238 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/823864 ,  H01L27/0251 ,  H01L27/0266 ,  H01L27/0922 ,  H01L27/10873 ,  H01L29/78

摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatoc protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.

摘要翻译： 本发明公开了一种半导体器件，其具有由静电场保护电路保护的内部电路，内部电路和静电保护电路形成在同一半导体衬底上。 内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。 内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。 单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入 第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。 作为本发明的另一个实施例，提供一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极 并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

公开(公告)号：US4803527A

公开(公告)日：1989-02-07

申请号：US876466

申请日：1986-06-20

申请人： Yasushi Hatta ,  Kazumichi Mitsusada ,  Hirotoshi Tanaka ,  Takehisa Hayashi

发明人： Yasushi Hatta ,  Kazumichi Mitsusada ,  Hirotoshi Tanaka ,  Takehisa Hayashi

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L21/8232 ,  H01L27/02 ,  H01L27/06 ,  H01L29/90 ,  H01L29/78

CPC分类号： H01L27/0605 ,  H01L27/0251

摘要： Disclosed is a semiconductor integrated circuit device forming MESFETs by use of a semi-insulator GaAs substrate which prevents destruction of an electrostatic destruction protect circuit and a Schottky junction of an internal circuit by causing a part of electrostatic energy, which is applied to external terminals, to flow from a semiconductor region connected to the external terminals into another semiconductor region which is formed in the vicinity of the semiconductor region described above and to which a predetermined fixed potential is applied.

摘要翻译： 公开了一种通过使用半绝缘体GaAs衬底形成MESFET的半导体集成电路器件，其通过施加施加到外部端子的一部分静电能来防止静电破坏保护电路和内部电路的肖特基结的破坏， 从连接到外部端子的半导体区域流到形成在上述半导体区域附近并且施加预定固定电位的另一个半导体区域。

公开(公告)号：US4630095A

公开(公告)日：1986-12-16

申请号：US626200

申请日：1984-06-29

申请人： Kanji Otsuka ,  Kunizou Sahara ,  Masao Sekibata ,  Kazumichi Mitsusada ,  Katsumi Ogiue

发明人： Kanji Otsuka ,  Kunizou Sahara ,  Masao Sekibata ,  Kazumichi Mitsusada ,  Katsumi Ogiue

IPC分类号： H01L23/02 ,  H01L23/057 ,  H01L23/26 ,  H01L23/31 ,  H01L23/556 ,  H01L23/10 ,  H01L23/04 ,  H01L23/16 ,  H01L23/30

CPC分类号： H01L23/26 ,  H01L23/057 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/556 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/8592 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/0102 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/1617 ,  H01L2924/16195 ,  H01L2924/3025

摘要： A packaged semiconductor device structure includes a semiconductor chip with an organic material covering thereon. The semiconductor chip is placed in a package and hermetically sealed with a low melting point glass. The organic covering serve to suppress undesirable influence on the semiconductor chip by .alpha.-rays which may be radiated from the package, and a getter material is placed in the package for decreasing undesirable gases in the package which may be emitted by the organic covering during the sealing process.

摘要翻译： 封装的半导体器件结构包括其上覆盖有机材料的半导体芯片。 将半导体芯片放置在封装中并用低熔点玻璃密封。 有机覆盖物用于通过可以从封装辐射的α-射线来抑制对半导体芯片的不期望的影响，并且将吸气剂材料放置在包装中以减少包装中的不期望的气体，这可能由有机覆盖物在 密封过程。

公开(公告)号：US4219369A

公开(公告)日：1980-08-26

申请号：US931007

申请日：1978-08-04

申请人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

发明人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/388 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/26

CPC分类号： H01L21/388 ,  H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/76216 ,  H01L21/76232 ,  H01L21/8222 ,  Y10S148/117 ,  Y10S148/143

摘要： The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.

摘要翻译： 本发明涉及一种制造半导体集成电路器件的方法，其目的在于减小将相邻半导体元件彼此隔离的隔离区的尺寸。 本发明的方法具有以下步骤：在衬底上形成不同导电类型的扩散杂质的沉积层与衬底的沉积层，在沉积层上形成具有孔的掩模膜，通过使用掩模膜进行蚀刻 作为扩散掩模，以蚀刻沉积层和基板下面的部分，从而形成将沉积层分成岛状沉积层部分的凹槽，并且将每个岛状沉积层中的杂质拉伸和扩散 沉积层部分以形成构成半导体元件的一部分的扩散层。

公开(公告)号：US4541003A

公开(公告)日：1985-09-10

申请号：US388216

申请日：1982-06-14

申请人： Kanji Otsuka ,  Kazumichi Mitsusada ,  Masao Sekibata ,  Shinji Ohnishi

发明人： Kanji Otsuka ,  Kazumichi Mitsusada ,  Masao Sekibata ,  Shinji Ohnishi

IPC分类号： H01L23/02 ,  H01L21/26 ,  H01L21/314 ,  H01L23/057 ,  H01L23/24 ,  H01L23/556 ,  H01L27/10 ,  G11C11/40 ,  H01L23/08 ,  H01L27/04

CPC分类号： H01L23/556 ,  H01L21/26 ,  H01L23/057 ,  H01L23/24 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/1617 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/3025

摘要： The present invention relates to a semiconductor device having a semiconductor element which is sealed by a ceramic package, wherein a shielding member is provided near it from upper surface of the semiconductor element to shield the alpha-particles radiated from the package.

摘要翻译： 本发明涉及一种具有由陶瓷封装密封的半导体元件的半导体器件，其中屏蔽部件从半导体元件的上表面附近设置，以遮蔽从封装辐射的α粒子。