发明授权
- 专利标题: Series-parallel type A-D converter for realizing high speed operation and low power consumption
- 专利标题(中): 串并联型A-D转换器,实现高速运行和低功耗
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申请号: US264676申请日: 1994-06-23
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公开(公告)号: US5539406A公开(公告)日: 1996-07-23
- 发明人: Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki
- 申请人: Hiroyuki Kouno , Toshio Kumamoto , Takahiro Miki
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX5-164862 19930702; JPX6-091335 19940428
- 主分类号: H03M1/06
- IPC分类号: H03M1/06 ; H03M1/14 ; H03M1/36 ; H03M1/76 ; H03M1/12
摘要:
An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.