摘要:
A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.
摘要:
The present invention is directed to improvement of a differential amplifier an its peripheral components employed in an A/D converter to enhance an accuracy of the A/D converter. The differential amplifier has an amplifying element comprised of a pair of differential transistors Q1 and Q2, emitter resistances 2a and 2b, and collector resistances 2c and 2d. The differential amplifier has transistors Q3 and Q4 constituting an emitter follower for applying an output amplified in the differential amplifying element to the outside. The differential amplifier includes transistors Q5 and Q6 having their respective base electrodes connected to input terminals 4a and 4b and serially connected to the transistors Q3 and Q4, and resistances 2e and 2f interposed between emitter electrodes of the transistors Q5 and Q6 so as to relieve any influence of variations in base-emitter voltages of the transistors Q3 and Q4. Effectively an output from the emitter follower can be improved and a gain of the differential amplifier and linearity can be also improved.
摘要:
In order to obtain a constant current circuit which has an excellent constant current property and requires no plural bias circuits, a base of an NPN bipolar transistor (5) and a gate of an N-channel MOS transistor (6) are connected to a first terminal (1) in common. A collector of the transistor (5) is connected to a second terminal (2) and a source of a transistor (6) is connected to a third terminal respectively, while a voltage source (59) is connected between the first and third terminals. An emitter of the transistor (5) is connected with a drain of the transistor (6). Identical bias voltages are supplied to the base and the gate, while a gate-to-drain voltage of the transistor (6) is equal to a base-to-emitter voltage of the transistor (5). Thus, the transistor (6) operates in a pentode region, to serve as a constant current load for the transistor (5).
摘要:
An improved differential subtracter 3a and an improved D/A converter 7a are used in a two-step parallel A/D converter 100. The D/A converter is responsive to complementary signals S1-S2 and B1-Bn indicative of results of conversion of higher bits to draw subtraction currents Is1 and Is2 through emitter electrodes of npn transistors Q1 and Q2. Since a difference between emitter currents I.sub.E1 and I.sub.E2 is small, base-emitter voltages V.sub.BE1 and V.sub.BE2 are substantially equal to each other. As a result, the A/D converter can execute the subtraction at high speed with high accuracy.
摘要:
An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.
摘要:
A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.
摘要:
An analog voltage subtracting circuit for calculating a difference between an analog input voltage and a voltage drop caused by a load includes an analog voltage generator 7 for generating an analog voltage, a load 3 having one end connected to an output of the analog voltage generator 7 and the other end connected to an output terminal 2, and a D/A converter 6 applying a positive output current Iout for generating a desired voltage drop at said the other end 4 of the load 3 and for applying a complementary output current Iout complementary to the positive output current Iout to said one end of the load 3. By this structure, a constant current of Iout+Iout flows at said one end 4 of the load 3, and therefore linear output can be provided.
摘要:
A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).
摘要:
An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.
摘要:
Positive and negative output ends of a differential circuit in a sample hold circuit are connected to capacitors through switch circuits. Further, collectors of two input transistors of a buffer circuit connected to the sample hold circuit are driven by a collector driving differential circuit, so as to make the collector.multidot.base voltages of two input transistors same to each other. Consequently, a stable sample hold circuit having an arbitrary gain can be provided. In addition, drifts of outputs from two capacitors in the sample hold circuit can be made equal to each other by the buffer circuit.