A testable memory array (34) has a plurality of TAG-DATA field pairs. Each TAG asserts a MATCHLINE signal if an input tag matches a stored tag. During normal operation, the asserted matchline signal causes the entry to outputs its DATA field. During a testing mode, testing circuitry (50 and 52) gates the matchline signal with the output of a one-of-N decoder (48). Consequently, only one of the various matchline signals can be asserted at any given time regardless of whether test data creates multiple tag matches. The various TAG bit cells can then be connected in scan chains without risk of driving two different DATA FIELDS to the same output bit line.