发明授权
US5554558A Method of making high precision w-polycide-to-poly capacitors in
digital/analog process
失效
在数字/模拟过程中制造高精度w-polycide-to-poly电容器的方法
- 专利标题: Method of making high precision w-polycide-to-poly capacitors in digital/analog process
- 专利标题(中): 在数字/模拟过程中制造高精度w-polycide-to-poly电容器的方法
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申请号: US387081申请日: 1995-02-13
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公开(公告)号: US5554558A公开(公告)日: 1996-09-10
- 发明人: Shun-Liang Hsu , Jyh-Kang Ting , Chun-Yi Shih
- 申请人: Shun-Liang Hsu , Jyh-Kang Ting , Chun-Yi Shih
- 申请人地址: TWX Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company
- 当前专利权人: Taiwan Semiconductor Manufacturing Company
- 当前专利权人地址: TWX Hsin-Chu
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L21/3105 ; H01L27/06 ; H01L21/70 ; H01L27/00
摘要:
A method for making a polycide-to-polysilicon capacitor, which has a reduced IPO thickness and low voltage coefficient, is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor. An oxide layer is formed over the bottom plate. The oxide layer is densified. A second layer of doped polysilicon is formed over the oxide layer. The second layer of polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric, and, finally, the bottom plate is annealed.
公开/授权文献
- US4980019A Etch-back process for failure analysis of integrated circuits 公开/授权日:1990-12-25
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