发明授权
US5557568A Non-volatile semiconductor memory device with verify mode for verifying
data written to memory cells
失效
具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
- 专利标题: Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells
- 专利标题(中): 具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
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申请号: US427265申请日: 1995-04-24
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公开(公告)号: US5557568A公开(公告)日: 1996-09-17
- 发明人: Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
- 申请人: Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX5-074797 19930331; JPX6-10209 19940201
- 主分类号: G11C17/00
- IPC分类号: G11C17/00 ; G11C7/02 ; G11C7/10 ; G11C16/02 ; G11C16/06 ; G11C16/10 ; G11C16/34 ; H01L21/8247 ; H01L27/115 ; G11C7/00
摘要:
A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
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