When a pad is connected to ground and a mode switching signal MHYP attains an L level, an integrated semiconductor device attains an FP mode. Following the transition of an internal column address strobe signal ZCASF and an internal write enable signal ZWEF to an L level, an NOR gate is opened to allow entry of internal data. When the pad is connected to a power supply potential and the mode selecting signal MHYP attains an H level, the integrated semiconductor device attains an EDO mode. The NOR gate is opened when the internal row address strobe signal ZRASF attains an L level, whereby the external data is entered. The writing operation in an EDO mode can be increased in speed.