公开(公告)号：US08218560B2

公开(公告)日：2012-07-10

申请号：US11791833

申请日：2005-11-01

申请人： Yasushi Fujinami ,  Goro Hayakawa

发明人： Yasushi Fujinami ,  Goro Hayakawa

IPC分类号： H04L12/28

CPC分类号： H04N21/4341 ,  H04N19/44 ,  H04N21/2368 ,  H04N21/42615 ,  H04N21/42646 ,  H04N21/434 ,  H04N21/44004

摘要： Disclosed is a demultiplexer for demultiplexing a multiplexed stream, obtained on time division multiplexing a plurality of elementary streams. A buffer controller, forming this demultiplexer, writes a multiplexed stream, beginning from a location specified by a data write pointer of a ring buffer, configured for storing data of the multiplexed stream, in the manner of an endless loop. On receipt of an ES1 readout request, an ES1 readout control unit takes out, from an ES1 readout pointer storage unit, a readout pointer, as a start point of retrieving an area in the ring buffer where the oldest ES1 is stored. The ES1 readout control unit then retrieves and reads out the ES1, with a location specified by the ES1 readout pointer, as a start point, and sends the ES1, thus read out, to the source of the request. The ES1 readout control unit then updates the ES1 readout pointer and the data leading end pointer.

摘要翻译： 公开了一种解复用器，用于对通过时分多路复用多个基本流而获得的复用流进行解复用。 形成该多路分解器的缓冲器控制器以无限循环的方式，从配置用于存储多路复用流的数据的环形缓冲器的数据写指针指定的位置开始写入多路复用流。 在接收到ES1读出请求时，ES1读出控制单元从ES1读出指针存储单元取出读出指针作为检索存储最早ES1的环形缓冲器中的区域的起始点。 然后，ES1读出控制单元以ES1读出指针指定的位置取出并读出ES1作为起始点，并将ES1发送到请求的源。 然后，ES1读出控制单元更新ES1读出指针和数据前端指针。

公开(公告)号：US07584511B2

公开(公告)日：2009-09-01

申请号：US11148795

申请日：2005-06-09

申请人： Yasushi Fujinami ,  Takenori Ohshima ,  Goro Hayakawa ,  Toshiya Hamada

发明人： Yasushi Fujinami ,  Takenori Ohshima ,  Goro Hayakawa ,  Toshiya Hamada

IPC分类号： G06F1/26 ,  G06F11/00 ,  G08B13/00

CPC分类号： G11B20/00086 ,  G11B20/00731 ,  G11B2020/10666 ,  G11B2020/10759

摘要： At step S372, permission information about video data that are being reproduced is obtained from permission information that represents whether video data corresponding to encoded video data equal to or larger than an access unit are permitted to be secondarily used. At step S373, it is determined whether the video data that are being reproduced have been permitted to be secondarily used corresponding to the permission information. When it has been determined that the video data that are being reproduced have been permitted to be secondarily used, at step S376, the video data that are being reproduced are captured. At step S381, a process using the captured video data is executed. The present invention can be applied to for example a game device that uses a DVD.

摘要翻译： 在步骤S372中，从表示是否允许对等于或大于访问单元的编码视频数据的视频数据进行二次使用的许可信息获得关于正在再现的视频数据的许可信息。 在步骤S373中，确定是否已经允许根据许可信息二次使用正被再现的视频数据。 当已经确定正被再现的视频数据已经被允许被二次使用时，在步骤S376，捕获正被再现的视频数据。 在步骤S381，执行使用所捕获的视频数据的处理。 本发明可以应用于例如使用DVD的游戏装置。

公开(公告)号：US20080013562A1

公开(公告)日：2008-01-17

申请号：US11791833

申请日：2005-11-01

申请人： Yasushi Fujinami ,  Goro Hayakawa

发明人： Yasushi Fujinami ,  Goro Hayakawa

IPC分类号： H04L12/54

CPC分类号： H04N21/4341 ,  H04N19/44 ,  H04N21/2368 ,  H04N21/42615 ,  H04N21/42646 ,  H04N21/434 ,  H04N21/44004

摘要： Disclosed is a demultiplexer for demultiplexing a multiplexed stream, obtained on time division multiplexing a plurality of elementary streams. A buffer controller, forming this demultiplexer, writes a multiplexed stream, beginning from a location specified by a data write pointer of a ring buffer, configured for storing data of the multiplexed stream, in the manner of an endless loop. On receipt of an ES1 readout request, an ES1 readout control unit takes out, from an ES1 readout pointer storage unit, a readout pointer, as a start point of retrieving an area in the ring buffer where the oldest ES1 is stored. The ES1 readout control unit then retrieves and reads out the ES1, with a location specified by the ES1 readout pointer, as a start point, and sends the ES1, thus read out, to the source of the request. The ES1 readout control unit then updates the ES1 readout pointer and the data leading end pointer.

摘要翻译： 公开了一种解复用器，用于对通过时分多路复用多个基本流而获得的复用流进行解复用。 形成该多路分解器的缓冲器控制器以无限循环的方式，从配置用于存储多路复用流的数据的环形缓冲器的数据写指针指定的位置开始写入多路复用流。 在接收到ES 1读出请求时，ES1读出控制单元从ES 1读出指针存储单元取出读出指针，作为检索存储了最早ES1的环形缓冲器中的区域的起始点 。 然后，ES1读出控制单元将由ES 1读出指针指定的位置的ES 1取出并读出作为起始点，并将ES1发送到请求的源。 然后，ES 1读出控制单元更新ES 1读出指针和数据前端指针。

公开(公告)号：US06538936B2

公开(公告)日：2003-03-25

申请号：US09887167

申请日：2001-06-25

申请人： Koji Tanaka ,  Goro Hayakawa

发明人： Koji Tanaka ,  Goro Hayakawa

IPC分类号： G11C700

CPC分类号： G11C29/02

摘要： A pump circuit forming a boosted power supply (Vpp) generating circuit includes: first and second pumps generating a boosted power supply; and a test circuit controlling levels of stress applied to the first and second pumps in accordance with a signal input from a ring oscillator and a test signal. A semiconductor memory device of the present invention enables application of a desired level of stress to each capacitor of the pump circuit formed for a stress test, and provides enhanced efficiency of the stress test and increased reliability of the semiconductor integrated circuit.

公开(公告)号：US5619457A

公开(公告)日：1997-04-08

申请号：US589687

申请日：1996-01-22

申请人： Goro Hayakawa ,  Yasuhiko Tsukikawa

发明人： Goro Hayakawa ,  Yasuhiko Tsukikawa

IPC分类号： G11C11/403 ,  G11C7/22 ,  G11C11/406 ,  G11C11/34

CPC分类号： G11C7/22 ,  G11C11/406

摘要： A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.

摘要翻译： 第一逻辑门电路接收内部行选通信号，内部列选通信号和用于提供操作状态检测信号的自刷新模式。 当处于待机状态和自刷新状态时，操作状态检测信号达到H电平。 当操作状态检测信号达到H电平时，第二CMOS逻辑门电路闭合。 因此，外部输入/输出控制信号不会发送到内部电路，并且直流电流不会流入CMOS逻辑门，而与外部输入/输出控制信号的电平无关。

公开(公告)号：US06285617B1

公开(公告)日：2001-09-04

申请号：US09556775

申请日：2000-04-25

申请人： Takashi Itou ,  Goro Hayakawa

发明人： Takashi Itou ,  Goro Hayakawa

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A refresh operation is started in response to activation of a refresh control signal. The refresh control circuit controls activation of a refresh control signal in accordance with a signal level of a row address decode enable signal in addition to signal levels of control signals activated in response to activation of signals /CAS and /RAS necessary for detecting the start of a CBR refresh operation. The row address decode enable signal is an internal control signal activated upon activation of a signal /RAS and maintained in an active state until signal /RAS is inactivated. As a result, the refresh control signal is not erroneously activated during normal operation even when a noise is caused to signal /RAS.

摘要翻译： 响应于刷新控制信号的激活而开始刷新操作。 刷新控制电路根据行地址解码使能信号的信号电平来控制刷新控制信号的激活，除了响应于检测启动信号所必需的信号/ CAS和/ RAS的激活而激活的控制信号的信号电平之外 CBR刷新操作。 行地址解码使能信号是在激活信号/ RAS时激活的内部控制信号，并且保持在活动状态，直到信号/ RAS被去激活。 结果，即使当使信号/ RAS发生噪声时，刷新控制信号也不会在正常操作期间被错误地激活。

公开(公告)号：US5563840A

公开(公告)日：1996-10-08

申请号：US559701

申请日：1995-11-15

申请人： Goro Hayakawa ,  Yasuhiko Tsukikawa

发明人： Goro Hayakawa ,  Yasuhiko Tsukikawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C13/00

CPC分类号： G11C7/1024 ,  G11C7/1045

摘要： When a pad is connected to ground and a mode switching signal MHYP attains an L level, an integrated semiconductor device attains an FP mode. Following the transition of an internal column address strobe signal ZCASF and an internal write enable signal ZWEF to an L level, an NOR gate is opened to allow entry of internal data. When the pad is connected to a power supply potential and the mode selecting signal MHYP attains an H level, the integrated semiconductor device attains an EDO mode. The NOR gate is opened when the internal row address strobe signal ZRASF attains an L level, whereby the external data is entered. The writing operation in an EDO mode can be increased in speed.

摘要翻译： 当焊盘连接到地并且模式切换信号MHYP达到L电平时，集成半导体器件达到FP模式。 在将内部列地址选通信号ZCASF和内部写使能信号ZWEF转换为L电平之后，打开NOR门以允许内部数据的输入。 当焊盘连接到电源电位并且模式选择信号MHYP达到H电平时，集成半导体器件达到EDO模式。 当内部行地址选通信号ZRASF达到L电平时，或非门被打开，从而进入外部数据。 EDO模式下的写入操作可以提高速度。

公开(公告)号：US20060021060A1

公开(公告)日：2006-01-26

申请号：US11148795

申请日：2005-06-09

申请人： Yasushi Fujinami ,  Takenori Ohshima ,  Goro Hayakawa ,  Toshiya Hamada

发明人： Yasushi Fujinami ,  Takenori Ohshima ,  Goro Hayakawa ,  Toshiya Hamada

IPC分类号： H04N7/16

CPC分类号： G11B20/00086 ,  G11B20/00731 ,  G11B2020/10666 ,  G11B2020/10759

摘要： At step S372, permission information about video data that are being reproduced is obtained from permission information that represents whether video data corresponding to encoded video data equal to or larger than an access unit are permitted to be secondarily used. At step S373, it is determined whether the video data that are being reproduced have been permitted to be secondarily used corresponding to the permission information. When it has been determined that the video data that are being reproduced have been permitted to be secondarily used, at step S376, the video data that are being reproduced are captured. At step S381, a process using the captured video data is executed. The present invention can be applied to for example a game device that uses a DVD.

公开(公告)号：US06366517B1

公开(公告)日：2002-04-02

申请号：US09062590

申请日：1998-04-20

申请人： Mitsunori Tsujino ,  Goro Hayakawa

发明人： Mitsunori Tsujino ,  Goro Hayakawa

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A semiconductor integrated circuit includes: first and second counters activated upon receipt of a low level signal and outputting a signal with a period which is twice that of the signal input; first fuse circuits connected to first counters; and a second fuse circuit connected to second counter. First counters are inactivated when fuses included in first fuse circuits are disconnected, and second counter is activated when a fuse included in second fuse circuit is disconnected. Thus, the period of a signal for determining a refresh period can be efficiently adjusted. Here, the arrangement of first fuse circuits and a second fuse circuit can be converse.

摘要翻译： 半导体集成电路包括：第一和第二计数器在接收到低电平信号时被激活，并输出信号的周期是信号输入的两倍; 连接到第一计数器的第一熔丝电路; 以及连接到第二计数器的第二熔丝电路。 当第一个熔断器电路中包含的保险丝断开时，第一个计数器失效，当第二个保险丝电路中的保险丝断开时，第二个计数器被激活。 因此，可以有效地调整用于确定刷新周期的信号的周期。 这里，第一熔丝电路和第二熔丝电路的布置可以相反。

公开(公告)号：US6034904A

公开(公告)日：2000-03-07

申请号：US35989

申请日：1998-03-06

申请人： Osamu Kuromiya ,  Susumu Tanida ,  Goro Hayakawa

发明人： Osamu Kuromiya ,  Susumu Tanida ,  Goro Hayakawa

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C29/12 ,  G11C29/14 ,  G11C29/50 ,  G11C8/00

CPC分类号： G11C29/50 ,  G11C29/14 ,  G11C11/401

摘要： A semiconductor memory device includes a control circuit, a test mode control circuit, an internal period setting circuit and an address latch circuit. The control circuit detects whether test mode is designated or not. The test mode control circuit detects whether or not self disturb test mode is designated. The internal period setting circuit repeatedly generates a clock signal of a prescribed period when the test mode and the self disturb test mode are designated. Simultaneously, the address latch circuit latches an address at a fall of a row address strobe signal. The row decoder is activated in response to the clock signal, and repeatedly sets the word line corresponding to the latched address to the selected state.

摘要翻译： 半导体存储器件包括控制电路，测试模式控制电路，内部周期设置电路和地址锁存电路。 控制电路检测是否指定测试模式。 测试模式控制电路检测是否指定了自身干扰测试模式。 当指定测试模式和自我干扰测试模式时，内部周期设置电路重复地产生规定周期的时钟信号。 同时，地址锁存电路在行地址选通信号的下降时锁存地址。 行解码器响应于时钟信号被激活，并且将对应于锁存地址的字线重复设置为所选择的状态。