发明授权
US5564056A Method and apparatus for zero extension and bit shifting to preserve
register parameters in a microprocessor utilizing register renaming
失效
用于零扩展和位移的方法和装置，以在使用寄存器重命名的微处理器中保留寄存器参数
- 专利标题： Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
- 专利标题（中）： 用于零扩展和位移的方法和装置，以在使用寄存器重命名的微处理器中保留寄存器参数
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申请号： US333397申请日： 1994-11-02
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公开(公告)号： US5564056A公开(公告)日： 1996-10-08
- 发明人: Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Robert P. Colwell
- 申请人： Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Robert P. Colwell
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： G06F9/38
- IPC分类号： G06F9/38 ; G06F7/00
摘要：
Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.
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