发明授权
US5565799A On chip error detection circuit 失效
片上错误检测电路

On chip error detection circuit
摘要:
A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.
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