The present invention is a three-transistor (3-T) SRAM cell that is made up of a half latch in combination with a dynamic random access memory (DRAM) cell. In a DRAM cell, the "0" bit state is represented by a discharged cell capacitor--a stable state. The "1" bit state, on the other hand, is represented by a charged cell capacitor--an unstable state, since the capacitor leaks rapidly toward the discharged "0" bit state. The new 3-T SRAM cell incorporates a latch which maintains the charge on the cell capacitor when the cell is in a "1" bit state. The cell circuitry includes a cell access transistor coupled to a capacitor, a pull-down transistor, and a P-channel thin film transistor (TFT) which acts as the capacitor pull-up device, the gate of the P-channel TFT also being the drain of the pull-down transistor. A separate polycrystalline silicon layer functions as the substrate of the TFT pull-up device. The 3-T SRAM cell is one half the size of a 4-T SRAM cell and about twice the size of a DRAM cell.