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    Method of manufacturing devices having vertical junction edge
    2.
    发明授权
    Method of manufacturing devices having vertical junction edge 有权
    制造具有垂直接合边缘的器件的方法

    公开(公告)号：US08501602B2

    公开(公告)日：2013-08-06

    申请号：US13336516

    申请日：2011-12-23

    申请人： Fernando Gonzalez ,  Chandra Mouli

    发明人： Fernando Gonzalez ,  Chandra Mouli

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66636 ,  H01L21/2257 ,  H01L21/823481 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/7834

    摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

    摘要翻译： 用于形成诸如晶体管的器件的技术具有垂直的接合边缘。 更具体地说，在沟槽中形成浅沟槽并填充氧化物。 可以在氧化物中形成空穴并填充导电材料，例如掺杂的多晶硅。 在沟槽边缘处在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望性质的二极管延伸。

    METHOD FOR FORMING A SELF-ALIGNED ISOLATION STRUCTURE UTILIZING SIDEWALL SPACERS AS AN ETCH MASK AND REMAINING AS A PORTION OF THE ISOLATION STRUCTURE
    3.
    发明申请
    METHOD FOR FORMING A SELF-ALIGNED ISOLATION STRUCTURE UTILIZING SIDEWALL SPACERS AS AN ETCH MASK AND REMAINING AS A PORTION OF THE ISOLATION STRUCTURE 审中-公开
    用于形成隔离隔离层的自对准隔离结构的方法作为隔离层，并且作为隔离结构的一部分

    公开(公告)号：US20120208345A1

    公开(公告)日：2012-08-16

    申请号：US13454187

    申请日：2012-04-24

    申请人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

    发明人： Fernando Gonzalez ,  David Chapek ,  Randhir P.S. Thakur

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76237

    摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

    摘要翻译： 本发明涉及在半导体衬底中形成微电子结构的方法。 该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。 绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。 间隔物可以由绝缘材料形成。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。 保形材料的平面化可能遵循。

    Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure
    4.
    发明授权
    Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure 有权
    用于形成利用侧壁间隔物作为蚀刻掩模并保留为隔离结构的一部分的自对准隔离结构的方法

    公开(公告)号：US08173517B2

    公开(公告)日：2012-05-08

    申请号：US12828868

    申请日：2010-07-01

    申请人： Fernando Gonzalez ,  David L. Chapek ,  Randhir P. S. Thakur

    发明人： Fernando Gonzalez ,  David L. Chapek ,  Randhir P. S. Thakur

    IPC分类号： H01L21/764 ,  H01L29/00

    CPC分类号： H01L21/76237

    摘要： The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an oxide overlying a semiconductor substrate. Insulating material may be formed substantially conformably over the oxide and remaining portions of the dielectric material. Spacers may be formed from the insulating material. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal material may be formed substantially conformably over the spacer, over the remaining portions of the dielectric material, and substantially filling the isolation trench. Planarization of the conformal material may follow.

    摘要翻译： 本发明涉及在半导体衬底中形成微电子结构的方法。 该方法包括选择性地去除介电材料以暴露覆盖半导体衬底的氧化物的一部分。 绝缘材料可以基本上顺应地形成在电介质材料的氧化物和剩余部分上。 间隔物可以由绝缘材料形成。 隔离沟蚀刻遵循间隔物蚀刻。 可以执行隔离沟槽中的表面的可选热氧化，其可以任选地随后掺杂隔离沟槽的底部以进一步隔离隔离沟槽的任一侧上的相邻有源区。 可以在绝缘材料的剩余部分上基本上顺应地在间隔物上形成共形材料，并且基本上填充隔离沟槽。 保形材料的平面化可能遵循。

    Needle catheter
    5.
    发明授权
    Needle catheter 有权
    针导管

    公开(公告)号：US08152758B2

    公开(公告)日：2012-04-10

    申请号：US11841470

    申请日：2007-08-20

    申请人： Gregory Waimong Chan ,  Fernando Gonzalez ,  Thuhuong Thi Phan ,  Dwight A. Ambat ,  Manolo Lumauig ,  Mina W. Chow

    发明人： Gregory Waimong Chan ,  Fernando Gonzalez ,  Thuhuong Thi Phan ,  Dwight A. Ambat ,  Manolo Lumauig ,  Mina W. Chow

    IPC分类号： A61M29/00

    CPC分类号： A61M29/00

    摘要： An apparatus including an expandable body; at least one delivery cannula coupled to an exterior portion of the expandable body; a needle having a protuberance thereon disposed in a lumen of the at least one delivery cannula; a stop disposed in the lumen of the at least one delivery cannula at a position distal to the protuberance on the needle. A method including positioning a catheter assembly including at least one needle delivery device disposed in an at least one delivery cannula, the at least one delivery cannula having an exit end; modifying the shape of the catheter assembly to modify the orientation of the exit end of the at least one delivery cannula at a region of interest; and advancing the at least one needle delivery device beyond the exit end of the at least one delivery cannula according to a controlled orientation.

    摘要翻译： 一种包括可膨胀体的装置; 至少一个输送插管，其连接到所述可膨胀体的外部部分; 其上具有突起的针，其设置在所述至少一个输送插管的内腔中; 设置在所述至少一个输送套管的内腔中的位于远离所述针头上的突起的位置处的止动件。 一种方法，包括定位包括设置在至少一个输送插管中的至少一个针递送装置的导管组件，所述至少一个输送插管具有出口端; 改变导管组件的形状以改变感兴趣区域中至少一个输送插管的出口端的取向; 以及根据受控的取向将所述至少一个针输送装置推进到所述至少一个输送插管的出口端。

    Capacitor-less memory cells and cell arrays
    6.
    发明授权
    Capacitor-less memory cells and cell arrays 有权
    无电容的存储单元和单元阵列

    公开(公告)号：US07919800B2

    公开(公告)日：2011-04-05

    申请号：US11711449

    申请日：2007-02-26

    申请人： Fernando Gonzalez ,  Chandra V. Mouli

    发明人： Fernando Gonzalez ,  Chandra V. Mouli

    IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L27/088

    CPC分类号： G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

    摘要： A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

    摘要翻译： 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有源区的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

    Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
    7.
    发明授权
    Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell 有权
    将磁性隧道结集成在浮动栅极存储单元上方的半导体磁存储器

    公开(公告)号：US07852668B2

    公开(公告)日：2010-12-14

    申请号：US12360496

    申请日：2009-01-27

    申请人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

    发明人： Parag Banerjee ,  Terry Gafron ,  Fernando Gonzalez

    IPC分类号： G11C11/15

    CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C16/0483 ,  H01L27/11521

    摘要： A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.

    摘要翻译： 半导体磁存储器件具有形成在存储单元上的磁性隧道结。 存储单元具有由浮动栅极包围的控制栅极。 浮动栅极通过钉扎层耦合到磁性隧道结，该钉扎层保持结的下部磁性层的磁性取向。 耦合到控制栅极的选定字线的电流产生第一磁场。 通过单元选择线的电流产生与第一磁场正交的第二磁场。 这改变了结的上部磁性层的磁性取向以降低其电阻，从而允许编程/擦除线上的写入/擦除电压对浮动栅极进行编程/擦除。

    Localized biasing for silicon on insulator structures
    9.
    发明授权
    Localized biasing for silicon on insulator structures 有权
    硅绝缘体结构的局部偏置

    公开(公告)号：US07659152B2

    公开(公告)日：2010-02-09

    申请号：US10930001

    申请日：2004-08-30

    申请人： Fernando Gonzalez ,  John K. Zahurak

    发明人： Fernando Gonzalez ,  John K. Zahurak

    IPC分类号： H01L21/84

    CPC分类号： H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

    摘要翻译： 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。

    LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES
    10.
    发明申请
    LOCALIZED BIASING FOR SILICON ON INSULATOR STRUCTURES 有权
    绝缘子结构中硅的局部偏置

    公开(公告)号：US20100012995A1

    公开(公告)日：2010-01-21

    申请号：US12565294

    申请日：2009-09-23

    申请人： Fernando Gonzalez ,  John K. Zahurak

    发明人： Fernando Gonzalez ,  John K. Zahurak

    IPC分类号： H01L27/108 ,  H01L29/06

    CPC分类号： H01L21/84 ,  H01L27/0214 ,  H01L27/10858 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.

    摘要翻译： 绝缘体上硅器件具有形成在SOI的绝缘体层中的局部偏置结构。 局部偏置结构包括图案化导体，其向SOI的硅层的不同区域提供偏置信号。 导体凹陷到绝缘体层中以提供与硅层基本平坦的界面。 导体连接到偏置电压源。 在一个实施例中，提供分别连接到多个电压源的多个导体。 因此，硅层的不同区域被不同的偏置信号偏置。