发明授权
US5584001A Branch target buffer for dynamically predicting branch instruction
outcomes using a predicted branch history
失效
分支目标缓冲区，用于使用预测的分支历史动态预测分支指令结果
- 专利标题： Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history
- 专利标题（中）： 分支目标缓冲区，用于使用预测的分支历史动态预测分支指令结果
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申请号： US509331申请日： 1995-07-31
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公开(公告)号： US5584001A公开(公告)日： 1996-12-10
- 发明人: Bradley D. Hoyt , Glenn J. Hinton , Andrew F. Glew , Subramanian Natarajan
- 申请人： Bradley D. Hoyt , Glenn J. Hinton , Andrew F. Glew , Subramanian Natarajan
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： G06F9/38
- IPC分类号： G06F9/38 ; G06F9/00
摘要：
A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.
公开/授权文献
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