发明授权
US5588122A Universal buffered interface for coupling multiple processors memory
units, and I/O interfaces to a common high-speed interconnect
失效
通用缓冲接口,用于耦合多个处理器内存单元,以及I / O接口连接到一个通用的高速互连
- 专利标题: Universal buffered interface for coupling multiple processors memory units, and I/O interfaces to a common high-speed interconnect
- 专利标题(中): 通用缓冲接口,用于耦合多个处理器内存单元,以及I / O接口连接到一个通用的高速互连
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申请号: US260107申请日: 1994-06-15
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公开(公告)号: US5588122A公开(公告)日: 1996-12-24
- 发明人: Armando Garcia
- 申请人: Armando Garcia
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G06F13/24
- IPC分类号: G06F13/24 ; G06F13/36 ; G06F13/38 ; G06F13/40 ; G06F13/42 ; G06F15/16 ; G06F15/17
摘要:
A universal buffered interface (UBIF 34) couples a local bus (32) to a global bus (24) and supports, on the local bus, up to four nodes. The nodes may be comprised of processors (22a, 28a), memory banks, and/or I/O interfaces. Each processor has an associated private memory. The UBIF includes bidirectional, first-in-first-out (FIFO) buffers, or queues, for each node and operates in conjunction with a two-level bus hierarchy. The UBIF supports decoupled global memory (26) read requests and replies, supports decoupled, atomic read-modify-write operations to Global Memory, and block-read support for transferring contiguous blocks of global memory to processors or I/O interfaces. The UBIF also enables the use of an inter-processor communication (IPC) mechanism that enables any processor to send an interrupt to any other processor or processors in the system during a single global bus cycle. An interrupt mask is transferred over the address bus during a specially marked bus cycle, the interrupt mask identifying the processor or processors to be interrupted.
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