A microprocessor comprising an execution unit for performing arithmetic functions, a fetch unit for determining which entry is to be accessed, an issue unit for accessing the entry from storage in a memory, and an address generation unit for generating an address for that entry. Portions of the base and limit values used for generating the address are stored in separate segments. These separate portions are rearranged so as to form a segment having contiguous base and limit bits. The contiguous base and limit values are then stored in a register file. Copies of the base and limit are stored in control registers and broadcast to other units. Furthermore, a resettable null bit is stored in another register. In addition, the AGU includes a means for selecting a particular field of the register file and performing read/write operations on the selected file.