公开(公告)号：US20150178078A1

公开(公告)日：2015-06-25

申请号：US14138054

申请日：2013-12-21

Applicant: H. Peter Anvin ,  Scott D. Rodgers

Inventor： H. Peter Anvin ,  Scott D. Rodgers

IPC: G06F9/30 ,  G06F9/34

CPC classification number: G06F9/30032 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30189

Abstract: Instructions and logic provide base register swap status verification functionality. Embodiments include a processor having a first model specific register (MSR) to store a first base address corresponding to a segment for a first execution context and a second MSR to store a second base address corresponding to a segment for a second context. A third register stores a base register swap status field corresponding to the segment of the first and second contexts. A decode unit decodes a swap instruction and execution logic executes an exchange of the first MSR value and the second MSR value responsive to the swap instruction. The execution logic determines if said exchange of the first MSR value and the second MSR value completed successfully, and changes a value of the base register swap status field responsive to a determination that said exchange completed successfully.

Abstract translation: 说明和逻辑提供基本寄存器交换状态验证功能。 实施例包括具有第一模型特定寄存器（MSR）的处理器，用于存储对应于第一执行上下文的段的第一基地址和第二MSR，以存储对应于第二上下文的段的第二基地址。 第三寄存器存储对应于第一和第二上下文的段的基址寄存器交换状态字段。 解码单元解码交换指令，并且执行逻辑响应于交换指令执行第一MSR值和第二MSR值的交换。 执行逻辑确定第一MSR值和第二MSR值的所述交换是否成功完成，并且响应于所述交换成功完成的确定而改变基本寄存器交换状态字段的值。

公开(公告)号：US20130326519A1

公开(公告)日：2013-12-05

申请号：US13995317

申请日：2011-12-30

Applicant: Andrew V. Anderson ,  Gilbert Neiger ,  Scott D. Rodgers ,  Lawrence O. Smith, III ,  Richard A. Uhlig ,  Steven M. Bennett

Inventor： Andrew V. Anderson ,  Gilbert Neiger ,  Scott D. Rodgers ,  Lawrence O. Smith, III ,  Richard A. Uhlig ,  Steven M. Bennett

IPC: G06F9/455

CPC classification number: G06F9/45533

Abstract: Embodiments of apparatuses and methods for processing virtual machine control structure shadowing are disclosed. In one embodiment, an apparatus includes instruction hardware, execution hardware, and control logic. The instruction hardware is to receive instructions. A first instruction is to transfer the processor from a root mode to a non-root mode. The non-root mode is for executing guest software in a virtual machine, where the processor is the return to root mode upon the detection of a virtual machine exit event. A second instruction is to access a data structure for controlling a virtual machine. The execution hardware is to execute the instructions. The control logic is to cause the processor to access a shadow data structure instead of the data structure, without returning to the root mode for the access to be performed, when the second instruction is executed in the non-root mode.

Abstract translation: 公开了用于处理虚拟机控制结构阴影的装置和方法的实施例。 在一个实施例中，装置包括指令硬件，执行硬件和控制逻辑。 指令硬件是接收指令。 第一条指令是将处理器从根模式转移到非根模式。 非根模式用于在虚拟机中执行客户软件，其中处理器在检测虚拟机退出事件时返回到根模式。 第二条指令是访问用于控制虚拟机的数据结构。 执行硬件是执行指令。 当以非根模式执行第二指令时，控制逻辑是使处理器不用返回到执行访问的根模式而不是数据结构而不是数据结构。

公开(公告)号：US20130219152A1

公开(公告)日：2013-08-22

申请号：US13844471

申请日：2013-03-15

Applicant: James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

Inventor： James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Abstract translation: 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

公开(公告)号：US20130174147A1

公开(公告)日：2013-07-04

申请号：US13341891

申请日：2011-12-30

Applicant: Ravi L. Sahita ,  David M. Durham ,  Gilbert Neiger ,  Andrew V. Anderson ,  Scott D. Rodgers

Inventor： Ravi L. Sahita ,  David M. Durham ,  Gilbert Neiger ,  Andrew V. Anderson ,  Scott D. Rodgers

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45583

Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.

Abstract translation: 本公开的各种实施例可以描述用于减少由程序之间切换存储​​器页面许可视图而引起的系统延迟的方法，装置和系统，同时仍保护存储器的关键区域免受恶意软件的攻击。 可以公开和要求保护其他实施例。

公开(公告)号：US08464035B2

公开(公告)日：2013-06-11

申请号：US12641534

申请日：2009-12-18

Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

公开(公告)号：US08161269B2

公开(公告)日：2012-04-17

申请号：US13070908

申请日：2011-03-24

Applicant: James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

Inventor： James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Abstract translation: 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

公开(公告)号：US5749084A

公开(公告)日：1998-05-05

申请号：US634092

申请日：1996-04-17

Applicant: Kamla P. Huck ,  Scott D. Rodgers ,  Andrew F. Glew

Inventor： Kamla P. Huck ,  Scott D. Rodgers ,  Andrew F. Glew

IPC: G06F9/34 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/06

CPC classification number: G06F12/1036 ,  G06F12/0292

Abstract: A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.

Abstract translation: 一种具有地址生成单元（AGU）的处理器，用于生成与要获取的条目相对应的地址。 AGU包括用于存储地址段的段寄存器文件和用于重新排列第一地址段的不连续基地址和限制位位置的电路​​，以便生成具有连续顺序的所有基址和限制位的第二地址段。 AGU还包括用于执行单个微指令以对存储在段寄存器堆中的第二地址段的选定字段执行读和写操作的电路。

公开(公告)号：US5625788A

公开(公告)日：1997-04-29

申请号：US203790

申请日：1994-03-01

Applicant: Darrell D. Boggs ,  Scott D. Rodgers

Inventor： Darrell D. Boggs ,  Scott D. Rodgers

IPC: G06F9/38 ,  G06F9/00

CPC classification number: G06F9/3865 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

Abstract: An out-of-order microprocessor signals event occurrence and provides event handling information utilizing a novel instruction issued to an execution unit upon detection of the condition giving rise to the event. Event information includes the type of event and characteristic information and data for use by a coded routine which handles the event. A reorder buffer stores this information to facilitate event handling actions and state updates. A retirement control circuit of the microprocessor includes a posting mechanism for use by the event handling routine.

Abstract translation: 无序微处理器发出信号事件发生，并且在检测到引起事件的状况时，利用发给执行单元的新颖指令来提供事件处理信息。 事件信息包括处理事件的编码例程所使用的事件类型和特征信息和数据。 重新排序缓冲区存储此信息以便于事件处理动作和状态更新。 微处理器的退休控制电路包括一个由事件处理程序使用的发布机构。

公开(公告)号：US5537560A

公开(公告)日：1996-07-16

申请号：US203783

申请日：1994-03-01

Applicant: Darrell D. Boggs ,  Alan B. Kyker ,  Scott D. Rodgers

Inventor： Darrell D. Boggs ,  Alan B. Kyker ,  Scott D. Rodgers

IPC: G06F9/315 ,  G06F9/318 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30072 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3842

Abstract: The present invention provides a microinstruction for conditionally selecting one of two data values based upon control states of a processor. The microinstruction is preferably utilized in an out-of-order processor, although it may be used in conventional processors, to perform state dependent operations, including but not limited to privilege or mode sensitive instruction checking, privilege or mode sensitive algorithm execution and processor state updating. This is accomplished through the issuance from microcode to an execution unit upon decoding of a state dependent instruction a conditional move operation that takes advantage of condition resolving circuitry implemented within the execution unit. The execution unit's circuitry makes available processor state information in the form of result values that can be immediately used by the microinstruction upon its execution to resolve the conditions which it specifies. Upon immediate resolution of a specified condition, one of two values (or microcode temporary registers having values therein) is selected in order to properly complete the state dependent operation or to take other appropriate action such as posting a fault.

Abstract translation: 本发明提供一种微指令，用于基于处理器的控制状态有条件地选择两个数据值中的一个。 尽管可以在常规处理器中使用微指令来优化地使用微指令来执行状态依赖操作，包括但不限于特权或模式敏感指令检查，特权或模式敏感算法执行和处理器状态 更新。 这通过在对状态相关指令进行解码时从微码向执行单元发布而实现，该条件移动操作利用在执行单元内实现的条件解析电路。 执行单元的电路以结果值的形式提供处理器状态信息，可以在微指令执行时立即使用结果值来解决其指定的条件。 立即解决指定条件后，选择两个值之一（或其中具有值的微代码临时寄存器）之一，以便正确完成状态相关操作或采取其他适当的操作，如发布故障。

公开(公告)号：US5517651A

公开(公告)日：1996-05-14

申请号：US174714

申请日：1993-12-29

Applicant: Kamla Huck ,  Andrew F. Glew ,  Scott D. Rodgers

Inventor： Kamla Huck ,  Andrew F. Glew ,  Scott D. Rodgers

IPC: G06F9/355 ,  G06F9/38 ,  G06F11/07 ,  G06F11/22 ,  G06F9/42

CPC classification number: G06F9/342 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/22 ,  G06F9/355 ,  G06F9/3861

Abstract: A microprocessor contains an address generation unit, including a segment block, for loading descriptor data and a segment selector in a segment register. Two descriptor loads from a global descriptor table (GDT) and a local descriptor table (LDT) are executed. A 64 bit global descriptor from the GDT is loaded into a temporary register, and a 64 bit local descriptor from the LDT is also loaded into a separate temporary register. If a table indicator bit in the segment selector indicates use of the GDT, then the descriptor data from the GDT is selected. Alternatively, if the table indicator bit in the segment selector indicates the use of the LDT, then the descriptor data from the LDT is selected. The segment block splits the 64 bit descriptor data selected into two 32 bit quantities. The two 32 bit data quantities are input to a test programmable logic array (PLA). The test PLA checks for permission violations, or faults, and detects the need for special handling of the register segment load operation. If a fault violation occurs, the segment block signals a fault exception. If no fault is detected, then the segment block loads the two 32 bit descriptor data segments, along with the selector, into the appropriate segment register. If special handling is required, a conditional indirect branch is utilized to reach the handler.

Abstract translation: 微处理器包含地址生成单元，包括用于加载描述符数据的段块和段寄存器中的段选择器。 执行来自全局描述符表（GDT）和本地描述符表（LDT）的两个描述符加载。 来自GDT的64位全局描述符被加载到临时寄存器中，并且来自LDT的64位本地描述符也被加载到单独的临时寄存器中。 如果段选择器中的表指示符位指示使用GDT，则选择来自GDT的描述符数据。 或者，如果段选择器中的表指示符位指示使用LDT，则选择来自LDT的描述符数据。 段块将所选择的64位描述符数据分成两个32位数量。 两个32位数据量输入到测试可编程逻辑阵列（PLA）。 测试解决方案检查是否有权限违规或故障，并检测是否需要特殊处理寄存器段加载操作。 如果发生故障违规，则段阻止发生故障异常。 如果没有检测到故障，则段块将与选择器一起将两个32位描述符数据段加载到适当的段寄存器中。 如果需要特殊处理，则使用条件间接分支来到达处理程序。