发明授权
US5632025A Method for preventing multi-level cache system deadlock in a
multi-processor system
失效
防止多处理器系统中多级缓存系统死锁的方法
- 专利标题: Method for preventing multi-level cache system deadlock in a multi-processor system
- 专利标题(中): 防止多处理器系统中多级缓存系统死锁的方法
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申请号: US696788申请日: 1996-08-14
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公开(公告)号: US5632025A公开(公告)日: 1997-05-20
- 发明人: Joseph P. Bratt , John Brennan , Peter Y. T. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavaglia
- 申请人: Joseph P. Bratt , John Brennan , Peter Y. T. Hsu , William A. Huffman , Joseph T. Scanlon , Steve Ciavaglia
- 申请人地址: CA Mountain View
- 专利权人: Silicon Graphics, Inc.
- 当前专利权人: Silicon Graphics, Inc.
- 当前专利权人地址: CA Mountain View
- 主分类号: G06F12/08
- IPC分类号: G06F12/08 ; G06F12/14
摘要:
A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.