A membrane probe (10) for simultaneously testing two or more alternate columns or rows of integrated circuit chips (14) on the processing wafer (12) includes a flexible transparent and self planarizing membrane (22). The membrane includes circuit traces (26) and is carried by a substrate (16) defining parallel ports (18) corresponding to alternate columns or rows of circuit chips (14). Active test circuitry units (48) are mounted on the substrate (16) to perform test functions close to the site of testing. Two probes (10,110) are employed for testing each full wafer. One membrane probe (10) contains ports (18) and membrane segments (22) corresponding to one set of chips on the processing wafer, while the other probe (110) containing ports (18) and membrane segments (22) for the other interlaced set of chips on the wafer. Contact pads (34) are provided on areas of the membrane traces (26) to be visually registered through the membrane with contact pads of the chips under test. A test fixture insert (54) receives either membrane test probe (10, 110) and cooperatively forms a sealed chamber (80) in which pressurized gas urges the contact pads (34) against the contacts pads of the chips (14) for testing. Sufficient space on the surface of the test head (10,110) is provided for mounting active test circuit units (48) on the membrane test heads.