发明授权
- 专利标题： Method for manufacturing a semiconductor device having reduced resistance of diffusion layers and gate electrodes
- 专利标题（中）： 制造具有降低的扩散层和栅极电阻的半导体器件的方法
-
申请号： US454647申请日： 1989-12-21
-
公开(公告)号： US5654241A公开(公告)日： 1997-08-05
- 发明人: Masakazu Kakumu
- 申请人： Masakazu Kakumu
- 申请人地址： JPX
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX
- 优先权： JPX63-324925 19881223
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/225 ; H01L21/265 ; H01L21/28 ; H01L21/285 ; H01L21/336 ; H01L21/8238 ; H01L21/8244 ; H01L27/092 ; H01L21/441
摘要：
In a method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region, thereby forming metal silicide layers of low resistance on only the diffusion layers. In a further method for manufacturing a semiconductor device, metal ions are doped into the surface regions of diffusion layers or a diffusion layer forming region and the upper surface of a gate electrode. Then, the structure is subjected to a process to make a silicide, thereby forming metal silicide layers of low resistance on only the diffusion layers and the gate electrode.
公开/授权文献
信息查询
IPC分类:
