Invention Grant
- Patent Title: Process for forming a semiconductor device having field isolation
- Patent Title (中): 用于形成具有场隔离的半导体器件的工艺
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Application No.: US417524Application Date: 1995-04-06
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Publication No.: US5665633APublication Date: 1997-09-09
- Inventor: George R. Meyer
- Applicant: George R. Meyer
- Applicant Address: IL Schaumburg
- Assignee: Motorola, Inc.
- Current Assignee: Motorola, Inc.
- Current Assignee Address: IL Schaumburg
- Main IPC: H01L21/316
- IPC: H01L21/316 ; H01L21/76 ; H01L21/762 ; H01L23/544
Abstract:
Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, 180) within the field isolation region (72, 152, 172, 182). The trenches (52, 54) are filled with a material (62) that is polished or etched to form the planar field isolation region (72, 74, 152, 172, 182) where the wide, planar field isolation regions (72, 152, 172, 182) include the mesa(s) (76, 150, 170, 180). Etching can be used or by polishing with minimal, if any, dishing occurs because the widths of the trenches (52, 54) are kept relatively narrow (usually no more than five microns wide). Mesas (180) within a wide, planar field isolation region (182) can form linguistic characters to better identify the part number or mask set of the device. The planar field isolation region (72, 74, 152, 172, 182) can be formed near LOCOS-type field isolation regions when required for certain types of input protection circuits or high potential components.
Public/Granted literature
- US4959024A Shielding device for electric plug connectors Public/Granted day:1990-09-25
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