发明授权
- 专利标题: Memory device performance by delayed power-down
- 专利标题(中): 内存设备性能延迟掉电
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申请号: US560229申请日: 1995-11-21
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公开(公告)号: US5668769A公开(公告)日: 1997-09-16
- 发明人: Tim M. Coffman , Ronald J. Syzdek , Timothy J. Coots , Phat C. Truong , Sung-Wei Lin
- 申请人: Tim M. Coffman , Ronald J. Syzdek , Timothy J. Coots , Phat C. Truong , Sung-Wei Lin
- 申请人地址: TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: TX Dallas
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C7/22 ; G11C11/409 ; G11C7/00
摘要:
The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.
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