发明授权
US5680572A Cache memory system having data and tag arrays and multi-purpose buffer
assembly with multiple line buffers
失效
具有数据和标签数组的高速缓冲存储器系统以及具有多个行缓冲器的多用途缓冲器组件
- 专利标题: Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
- 专利标题(中): 具有数据和标签数组的高速缓冲存储器系统以及具有多个行缓冲器的多用途缓冲器组件
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申请号: US680109申请日: 1996-07-15
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公开(公告)号: US5680572A公开(公告)日: 1997-10-21
- 发明人: Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
- 申请人: Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F12/08
- IPC分类号: G06F12/08
摘要:
A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.
公开/授权文献
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