发明授权
- 专利标题： Wafer-scale techniques for fabrication of semiconductor chip assemblies
- 专利标题（中）： 制造半导体芯片组件的晶圆尺度技术
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申请号： US319966申请日： 1994-10-07
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公开(公告)号： US5685885A公开(公告)日： 1997-11-11
- 发明人: Igor Y. Khandros , Thomas H. Distefano
- 申请人： Igor Y. Khandros , Thomas H. Distefano
- 申请人地址： CA San Jose
- 专利权人： Tessera, Inc.
- 当前专利权人： Tessera, Inc.
- 当前专利权人地址： CA San Jose
- 主分类号： H01L21/60
- IPC分类号： H01L21/60 ; H01L21/822 ; H01L21/98 ; H01L23/13 ; H01L23/31 ; H01L23/485 ; H01L23/498 ; H01L23/58 ; H01L25/065 ; H01L25/16 ; H05K3/30
摘要：
Semiconductor chip assemblies are fabricated by assembling flexible, sheetlike elements bearing terminals to a wafer, connecting the terminals of each sheetlike element to contacts on the chip, and subsequently severing the chips from the wafer to provide individual assemblies. Each assembly includes a sheetlike element and a chip, arranged so that the terminals on the flexible element.
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