Invention Grant
- Patent Title: Method for fabricating semiconductor device having CMOS structure
- Patent Title (中): 制造具有CMOS结构的半导体器件的方法
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Application No.: US739781Application Date: 1996-10-30
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Publication No.: US5691225APublication Date: 1997-11-25
- Inventor: Hitoshi Abiko
- Applicant: Hitoshi Abiko
- Applicant Address: JPX Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JPX Tokyo
- Priority: JPX7-308355 19951031
- Main IPC: H01L21/265
- IPC: H01L21/265 ; H01L21/28 ; H01L21/285 ; H01L21/8238 ; H01L27/092 ; H01L21/70
Abstract:
A semiconductor device having a CMOS structure having a low resistivity silicide layer in a source/drain region is fabricated. To realize silicide formation for resistivity reduction of the n-type source/drain region, an impurity-free silicon layer is formed thereon before forming a high melting point metal silicide layer. For the n-type source/drain region, ion implantation is made through the silicon layer. It is thus possible to obtain a shallow junction of the p-type source/drain region, prevent ion implantation time increase and obtain quick fabrication without reducing the ion implantation energy.
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