发明授权
US5696924A Memory access circuit with address translation performing auto increment
of translated address on writes and return to translated address on
reads
失效
具有地址转换的存储器访问电路在写入时执行翻译地址的自动增量，并在读取时返回到翻译的地址
- 专利标题： Memory access circuit with address translation performing auto increment of translated address on writes and return to translated address on reads
- 专利标题（中）： 具有地址转换的存储器访问电路在写入时执行翻译地址的自动增量，并在读取时返回到翻译的地址
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申请号： US487750申请日： 1995-06-07
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公开(公告)号： US5696924A公开(公告)日： 1997-12-09
- 发明人: Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
- 申请人： Iain C. Robertson , Jeffrey L. Nye , Michael D. Asal , Graham B. Short , Richard D. Simpson , James G. Littleton
- 申请人地址： TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： TX Dallas
- 主分类号： G06F3/14
- IPC分类号： G06F3/14 ; G09G1/16 ; G09G5/00 ; G09G5/06 ; G09G5/36 ; G09G5/39 ; G09G5/395 ; G06F12/10
摘要：
A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.
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