公开(公告)号：US20080191910A1

公开(公告)日：2008-08-14

申请号：US12028469

申请日：2008-02-08

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: H03M7/16 ,  H03M1/12

CPC classification number: H03M7/16 ,  H03M7/165

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract translation: 本发明涉及格雷码及其转换为符号和幅度表示。 格雷码用于闪存ADC（模数转换器），将模拟波形转换为采样二进制值。 这可以通过温度计代码来实现，并且本发明解决了由于不确定的温度计代码值导致的误差传播的问题。 特别地，本发明提供了一种格雷码，用于符号和幅度转换器，其被布置为产生除了符号位之外的其输出的比特，对于格雷码的相同代码，其与来自符号位改变值的边界相同的距离 格雷码按照它们的价值排列。

公开(公告)号：US5636335A

公开(公告)日：1997-06-03

申请号：US479478

申请日：1995-06-07

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G06T15/60

CPC classification number: G06F3/1438 ,  G06F3/14 ,  G09G5/06 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126 ,  G09G5/001

Abstract: A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory. The second palette is connected to the graphics processor permitting it to specify the color data words stored in the second look-up table memory. An interface circuit connects to the host data bus, the host address bus and the second palette. The interface circuit writes data received from the host data bus into the second palette upon detecting predetermined addresses on the host address bus. This causes at least a portion of the second palette to store identical data as stored in corresponding locations of the first palette.

Abstract translation: 包括主计算机和图形处理器的图形计算机系统。 主机具有主机数据总线和主机地址总线。 第一视频存储器存储与显示相对应的颜色代码。 第一个视频存储器连接到主机，允许它指定颜色代码。 连接到第一视频存储器的第一调色板具有第一查找表存储器，用于调用与从第一视频存储器接收的彩色代码相对应的彩色数据字。 第一调色板连接到主计算机，允许其指定存储在第一查找表存储器中的颜色数据字。 图形处理器具有本地数据总线和本地地址总线。 第二视频存储器存储与显示相对应的颜色代码，图形处理器指定存储在第二视频存储器中的颜色代码。 连接到第二视频存储器的第二调色板具有第二查找表存储器。 第二调色板连接到图形处理器，允许其指定存储在第二查找表存储器中的颜色数据字。 接口电路连接到主机数据总线，主机地址总线和第二个调色板。 接口电路在检测到主机地址总线上的预定地址时，将从主机数据总线接收的数据写入第二调色板。 这导致第二调色板的至少一部分存储与存储在第一调色板的相应位置中相同的数据。

公开(公告)号：US5627568A

公开(公告)日：1997-05-06

申请号：US990971

申请日：1992-12-15

Applicant: Ian J. Sherlock ,  Richard D. Simpson ,  Michael D. Asal

Inventor： Ian J. Sherlock ,  Richard D. Simpson ,  Michael D. Asal

IPC: G09G5/36 ,  G09G5/39 ,  G09G5/00

CPC classification number: G09G5/39 ,  G09G5/363

Abstract: A display buffer includes a plurality of memory banks, each said bank having a plurality of ordered rows of data storage locations. Circuitry controls the storage of a plurality of sequenced lines of display data in said display buffer. A first set of lines of display data is stored at contiguous locations in a first memory bank with the first word of a first line being stored in a location offset from the first location of the first row so a last word of a last line is stored in the last location of the last row. A second set of lines is stored at contiguous locations starting at the first row of the second memory bank. A last line of the second set of lines is stored so that the last word of this last line is stored in the last location of a selected row of the second bank. A third set of lines is stored in a third memory bank starting at a memory line other than the first memory line. If additional space is needed, the display lines wrap around to the first location of the first line of the third bank of memories. A graphics processor may provide the memory addressing and bank selection logic.

Abstract translation: 显示缓冲器包括多个存储体，每个所述存储体具有多个排列的数据存储位置行。 电路控制在所述显示缓冲器中存储多条排序的显示数据行。 第一组显示数据被存储在第一存储体中的连续位置处，其中第一行的第一个字被存储在偏离第一行的第一位置的位置中，从而最后一行的最后一个字被存储 在最后一行的最后一个位置。 第二组线路存储在从第二存储器组的第一行开始的连续位置处。 存储第二组行的最后一行，使得最后一行的最后一个字被存储在第二组的所选行的最后位置。 第三组线路存储在从第一存储器线以外的存储线开始的第三存储体中。 如果需要额外的空间，则显示线缠绕到第三组存储器的第一行的第一位置。 图形处理器可以提供存储器寻址和存储体选择逻辑。

公开(公告)号：US5398316A

公开(公告)日：1995-03-14

申请号：US17566

申请日：1993-02-16

Applicant: Karl M. Guttag ,  Richard D. Simpson ,  Robert J. Gove

Inventor： Karl M. Guttag ,  Richard D. Simpson ,  Robert J. Gove

IPC: G06T1/60 ,  G06F15/62

CPC classification number: G06T1/60

Abstract: A processing system operating on data words having first and second portions includes a memory bank comprising first and second memories each with associated first and second set of address inputs. First memory includes a first storage location storing the first portion of a first word accessible by a set of address bits received at the first inputs and a second set of address bits received at the second inputs. The first memory further includes a second storage location storing the second portion of a second word accessible by the first set of bits received at the first inputs and a third set of bits received at the second inputs. Second memory includes a first storage location storing the second portion of the second word accessible by the first set of bits received at the first inputs and the second set of bits received at the second inputs. Second memory has a second storage location storing the first portion of the second word accessible by the first inputs and the third set of bits received at the second inputs. Processing system includes a processor operating in a first mode to access a selected one of the first and second words and in a second mode to access a selected one of the first and second portions of both the first and second words.

Abstract translation: 对具有第一和第二部分的数据字操作的处理系统包括存储器组，其包括第一和第二存储器，每个存储器具有相关联的第一和第二组地址输入。 第一存储器包括存储第一字的第一部分的第一存储位置，该第一字可由在第一输入处接收的一组地址位可访问，以及在第二输入处接收的第二组地址位。 第一存储器还包括第二存储位置，存储由在第一输入处接收的第一组位可访问的第二字的第二部分和在第二输入处接收的第三组位。 第二存储器包括存储第二字的第二部分的第一存储位置，该第二字可由在第一输入处接收的第一组位和第二输入端接收的第二组位可访问。 第二存储器具有存储由第一输入可访问的第二字的第一部分和在第二输入处接收的第三组位的第二存储位置。 处理系统包括以第一模式操作的处理器，以访问第一和第二字中的所选择的一个，并且以第二模式访问第一和第二字的第一和第二部分中的所选择的一个。

公开(公告)号：US5341470A

公开(公告)日：1994-08-23

申请号：US544779

申请日：1990-06-27

Applicant: Richard D. Simpson ,  Jeffrey L. Nye ,  Michael D. Asal

Inventor： Richard D. Simpson ,  Jeffrey L. Nye ,  Michael D. Asal

IPC: G09G5/02 ,  G09G5/06 ,  G09G5/12 ,  G09G5/36 ,  G09G5/39 ,  G06F15/62

CPC classification number: G09G5/12 ,  G09G5/06 ,  G09G5/363 ,  G09G5/39 ,  G09G2330/12 ,  G09G2360/123 ,  G09G5/022

Abstract: A computer graphics system. The system includes a video memory having a shift register adapted for split shift register transfers, and digital computer for controlling the video memory and having a tap point counter clocked by a shift clock signal and also having a blanking circuit with a blanking output. Further, logic circuitry enabled by the blanking output is connected to initiate an extra shift clock pulse for the tap point counter during a blanking interval. Other systems, palette devices, and methods are also disclosed.

Abstract translation: 计算机图形系统。 该系统包括具有适用于分离移位寄存器传输的移位寄存器的视频存储器，以及用于控制视频存储器并具有由移位时钟信号计时的分接点计数器的数字计算机，并且还具有带有消隐输出的消隐电路。 此外，由消隐输出使能的逻辑电路被连接以在消隐间隔期间启动分接点计数器的额外移位时钟脉冲。 还公开了其他系统，调色板装置和方法。

公开(公告)号：US5287470A

公开(公告)日：1994-02-15

申请号：US457992

申请日：1989-12-28

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G06F12/06 ,  G06T1/60 ,  G09G5/393 ,  G06F12/00

CPC classification number: G06F12/0607 ,  G09G5/393

Abstract: A circuit and method of operation for controlling block-write operations to interleaved memories is disclosed which includes first and second interleave banks of memories, each memory addressable in a normal mode in a block-write mode. Each memory has a plurality of input nodes for receiving data in a normal mode, ones of the input nodes operable to receive data in the block-write mode and other ones of said input nodes not used in the block-write mode. Coupling circuitry couples leads from an output bus to input nodes of the first bank memories which are operable to receive data in the block-write mode and to input nodes in the second bank of memories which are not used in the block-write mode.

Abstract translation: 公开了一种用于控制对交错存储器的块写入操作的电路和操作方法，其包括存储器的第一和第二交错存储器组，每个存储器以块写入模式在正常模式下可寻址。 每个存储器具有用于以正常模式接收数据的多个输入节点，所述输入节点中的一个可用于以块写入模式接收数据，而在块写入模式中不使用所述输入节点中的其他输入节点。 耦合电路将引线从输出总线耦合到第一组存储器的输入节点，第一组存储器可操作用于以块写入模式接收数据，并输入在块写入模式中未使用的第二存储器组中的节点。

公开(公告)号：US5233690A

公开(公告)日：1993-08-03

申请号：US387568

申请日：1989-07-28

Applicant: Ian J. Sherlock ,  Richard D. Simpson

Inventor： Ian J. Sherlock ,  Richard D. Simpson

IPC: G09G5/393

CPC classification number: G09G5/393

Abstract: A circuit controls the reordering of data as it is transferred to control a memory. The data to be reordered is presented such that the ordinate bit position within a data word is uniquely associated with a particular input to a data bus. The bus inputs, however, are connected to the VRAM in an arrangement contrary to the desired ordinate association with the compressed data word. A single swizzle logic circuit operates to allow graphic compressed data to be reordered for presentation to the block-write inputs of a VRAM regardless of the VRAM or pixel size. The circuit relies upon properly expanding the compressed data prior to the actual reordering of the ordinate positions of the data bits. A method for controlling the reordering of data also is described.

Abstract translation: 电路控制数据的重新排序，因为它被传送以控制存储器。 呈现要重新排序的数据，使得数据字中的纵坐标位置与数据总线的特定输入唯一地相关联。 然而，总线输入以与压缩数据字的期望的纵坐标相关联的布置连接到VRAM。 单个旋转逻辑电路用于允许图形压缩数据被重排序以呈现给VRAM的块写入输入，而不管VRAM或像素尺寸如何。 电路依赖于在数据位的纵坐标位置的实际重新排序之前适当地扩展压缩数据。 还描述了一种用于控制数据重新排序的方法。

公开(公告)号：US4992727A

公开(公告)日：1991-02-12

申请号：US373123

申请日：1989-06-28

Applicant: Richard D. Simpson ,  Iain C. Robertson

Inventor： Richard D. Simpson ,  Iain C. Robertson

IPC: G01R31/3185

CPC classification number: G01R31/318541

Abstract: A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data in the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor. During testing the series connected transistor is blocked and the first latch element is connected in a two elements per bit shift register configuration with the second latch element by series connected transistors controlled by antiphase square waves.

Abstract translation: 一种用于数字信号处理器的数字数据存储电路，其能够接收异步输入并且可通过选择性地将存储电路配置为移位寄存器来进行测试，从而能够输入和提取处理器中的测试数据。 存储电路包括两个锁存元件，每个锁存元件由以正反馈布置连接的两个互补晶体管反相器电路形成，其中第二反相器电路的输出电流能力被限制以使得锁存元件可响应于施加到 它。 异步输入通过开关装置施加到第一锁存元件，开关装置包括响应于CLEAR输入的与晶体管串联的SET输入的互补晶体管反相器。 互补逆变器通过串联连接的晶体管连接到第一锁存元件的输入。 在测试期间，串联连接的晶体管被​​阻塞，并且第一锁存元件以每位移位寄存器配置的两个元件连接，第二锁存元件通过由反相方波控制的串联连接的晶体管连接。

公开(公告)号：US4713748A

公开(公告)日：1987-12-15

申请号：US701827

申请日：1985-02-12

Applicant: Surendar S. Magar ,  Daniel L. Essig ,  Richard D. Simpson ,  Edward R. Caudel

Inventor： Surendar S. Magar ,  Daniel L. Essig ,  Richard D. Simpson ,  Edward R. Caudel

IPC: G06F9/315 ,  G06F13/00

CPC classification number: G06F9/3004 ,  G06F9/30032 ,  G06F9/30036

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program and data memory, with separate address and data paths for program and data. An external program address bus allows off-chip program fitch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program memory may be a RAM and this additional RAM may be configured as either program or data memory space. The processor may operate with all off-chip program memory and a large on-chip data memory, or with program execution from on-chip RAM (downloaded from off-chip program memory) using a block move instruction. A repeat instruction is used to save program space when using block-move, or multiply instructions as needed for digital filters or the like.

Abstract translation: 用于实时数字信号处理的系统采用具有单独的片上程序和数据存储器的单片微机器件，具有用于程序和数据的分开的地址和数据路径。 外部程序地址总线允许片外程序适应扩展模式，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单个状态16x16乘法功能，32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。 片上程序存储器可以是RAM，并且该附加RAM可以被配置为程序或数据存储器空间。 处理器可以利用所有片外程序存储器和大的片上数据存储器，或使用块移动指令从片上RAM（从片外程序存储器中下载）执行程序。 当使用块移动时，使用重复指令来节省程序空间，或者根据数字滤波器等的需要乘以指令。

公开(公告)号：US07642938B2

公开(公告)日：2010-01-05

申请号：US12028469

申请日：2008-02-08

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: H03M7/04

CPC classification number: H03M7/16 ,  H03M7/165

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract translation: 本发明涉及格雷码及其转换为符号和幅度表示。 格雷码用于闪存ADC（模数转换器），将模拟波形转换为采样二进制值。 这可以通过温度计代码来实现，并且本发明解决了由于不确定的温度计代码值导致的误差传播的问题。 特别地，本发明提供了一种格雷码，用于符号和幅度转换器，其被布置为产生除了符号位之外的其输出的比特，对于格雷码的相同代码，其与来自符号位改变值的边界相同的距离 格雷码按照它们的价值排列。