发明授权
US5758141A Method and system for selective support of non-architected instructions
within a superscaler processor system utilizing a special access bit
within a machine state register
失效
在利用机器状态寄存器内的特殊访问位的超标量处理器系统内选择性地支持非架构指令的方法和系统
- 专利标题: Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register
- 专利标题(中): 在利用机器状态寄存器内的特殊访问位的超标量处理器系统内选择性地支持非架构指令的方法和系统
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申请号: US386977申请日: 1995-02-10
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公开(公告)号: US5758141A公开(公告)日: 1998-05-26
- 发明人: James Allan Kahle , Albert J. Loper , Soummya Mallick , Aubrey Deene Ogden , John Victor Sell
- 申请人: James Allan Kahle , Albert J. Loper , Soummya Mallick , Aubrey Deene Ogden , John Victor Sell
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/318 ; G06F9/455
摘要:
A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.
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