公开(公告)号：US5758141A

公开(公告)日：1998-05-26

申请号：US386977

申请日：1995-02-10

申请人： James Allan Kahle ,  Albert J. Loper ,  Soummya Mallick ,  Aubrey Deene Ogden ,  John Victor Sell

发明人： James Allan Kahle ,  Albert J. Loper ,  Soummya Mallick ,  Aubrey Deene Ogden ,  John Victor Sell

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/455

CPC分类号： G06F9/30181 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/45554

摘要： A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.

摘要翻译： 一种用于允许在超标量处理器系统内选择性地支持非架构指令的方法和系统。 系统机器状态寄存器内的特殊访问位被提供和设置为响应于期望执行非架构指令的应用程序的每个启动。 此后，每当非架构化指令被解码时，确定特殊访问位的状态。 响应于特殊访问位的设置状态执行非架构指令。 如果未设置特殊访问位，则响应于非架构化指令的尝试执行而发出非法指令程序中断。 以这种方式，例如，复杂指令集计算（CISC）指令可以选择性地启用以在精简指令集计算（RISC）数据处理系统中执行，同时保持与精简指令集计算（RISC）指令的完全架构符合性。

公开(公告)号：US5764969A

公开(公告)日：1998-06-09

申请号：US387149

申请日：1995-02-10

申请人： James Allan Kahle ,  Albert J. Loper ,  Soummya Mallick ,  Aubrey Deene Ogden ,  John Victor Sell

发明人： James Allan Kahle ,  Albert J. Loper ,  Soummya Mallick ,  Aubrey Deene Ogden ,  John Victor Sell

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/14 ,  G06F9/44

CPC分类号： G06F9/461 ,  G06F12/1475

摘要： A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to "supervisor;" external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed. A disable special access (DSA) instruction is then executed which restores the bits within the machine state register which were modified during the ESA instruction. The ESA and DSA instructions are implemented without modifying the instruction stream by utilizing user level procedure calls, thereby reducing the overhead of the branch table necessary to determine the desired execution path.

摘要翻译： 一种用于在超标量数据处理系统中增强系统管理操作的方法和系统。 在受保护的存储器空间内执行所选特权操作的这些监督级指令首先被识别为不需要完整的上下文同步。 每次执行这样的指令时，执行使能特殊访问（ESA）指令作为该指令或指令组的入口点。 存储用于数据处理系统的机器状态寄存器的一部分，然后如下修改机器状态寄存器：设置问题位，将执行特权状态改变为“主管”; 外部中断被禁用; 并设置访问权限状态位; 并设置特殊访问模式位，允许执行特殊指令。 然后执行在受保护的存储器空间内执行所选择的特权操作的指令。 然后执行禁用特殊访问（DSA）指令，其恢复机器状态寄存器中在ESA指令期间被修改的位。 通过利用用户级过程调用来实现ESA和DSA指令而不修改指令流，从而减少确定所需执行路径所需的分支表的开销。

公开(公告)号：US5758140A

公开(公告)日：1998-05-26

申请号：US581793

申请日：1996-01-25

申请人： James Allan Kahle ,  Soummya Mallick

发明人： James Allan Kahle ,  Soummya Mallick

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/42

CPC分类号： G06F9/30167 ,  G06F9/30174

摘要： A system and method for improving the performance of a processor that emulates a guest instruction where the guest instruction includes a first and second operand. The first operand is stored in a general purpose register, and the second operand is stored in a special-purpose register. The method and system provides a host instruction that performs an operation using the first operand and the second operand without moving the second operand from the special-purpose register into the general purpose register. This reduces the number of instructions in the semantic routines necessary to operate on immediate data from guest instructions and increases emulation performance.

摘要翻译： 一种用于提高仿真访客指令的处理器的性能的系统和方法，其中所述访客指令包括第一和第二操作数。 第一个操作数存储在通用寄存器中，第二个操作数存储在专用寄存器中。 该方法和系统提供主机指令，其使用第一操作数和第二操作数执行操作，而不将第二操作数从专用寄存器移动到通用寄存器中。 这减少了从客户指令对即时数据进行操作所需的语义程序中的指令数量，并增加了仿真性能。

公开(公告)号：US5732235A

公开(公告)日：1998-03-24

申请号：US591291

申请日：1996-01-25

申请人： James Allan Kahle ,  Soummya Mallick ,  Larry Bryce Phillips ,  Russell Adley Reininger

发明人： James Allan Kahle ,  Soummya Mallick ,  Larry Bryce Phillips ,  Russell Adley Reininger

IPC分类号： G06F9/318 ,  G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/3879 ,  G06F9/45504

摘要： A system and method for reducing the cycle time necessary to execute semantic routines in a processor that emulates guest instructions. Each of the semantic routines includes a block of host instructions for performing the function of the corresponding guest instruction, and the last instruction in each of the semantic routines is a branch instruction. The method and system first determines the block length of each of the semantic routines. When a first guest instruction is encountered, the block of instructions in a first semantic routine corresponding to a guest instruction is executed. The block length of first semantic routine is then used to determine when to fetch a second semantic routine without fetching and decoding the branch instruction in the first semantic routine, thereby increasing emulation performance.

摘要翻译： 一种用于减少在模拟客户指令的处理器中执行语义例程所需的周期时间的系统和方法。 每个语义例程包括用于执行相应来宾指令的功能的主机指令块，并且每个语义例程中的最后一条指令是分支指令。 该方法和系统首先确定每个语义例程的块长度。 当遇到第一访客指令时，执行对应于访客指令的第一语义程序中的指令块。 然后，第一语义例程的块长度用于确定何时获取第二语义例程而不在第一语义例程中取出和解码分支指令，从而增加仿真性能。

公开(公告)号：US5850563A

公开(公告)日：1998-12-15

申请号：US526610

申请日：1995-09-11

申请人： Albert J. Loper ,  Soummya Mallick

发明人： Albert J. Loper ,  Soummya Mallick

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3838 ,  G06F9/3863

摘要： A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the general purpose registers, and the microprocessor's dispatch unit dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit. The method comprises the dispatch unit dispatching a multi-register instruction to the load/store unit to begin execution of the multi-register instruction, wherein the multi-register instruction, such as a store multiple or a load multiple, stores or loads data from more than one of the plurality of general purpose registers to memory, and further, prior to the multi-register instruction finishing execution in the load/store unit, the dispatch unit dispatches a floating-point instruction, which is dependent upon source operand data stored in one or more floating-point registers of the plurality of floating point registers, to the floating-point execution unit, wherein the dispatched floating-point instruction completes execution prior to the multi-register instruction finishing execution.

摘要翻译： 提供了在先前加载/存储多个指令之前的超标量微处理器中用于早期完成浮点指令的方法和装置。 微处理器的加载/存储执行单元向通用寄存器加载或存储数据，微处理器的调度单元将指令分派到包括加载/存储执行单元和浮点执行单元的多个执行单元。 该方法包括：调度单元向加载/存储单元分配多寄存器指令以开始执行多寄存器指令，其中多寄存器指令（例如存储器多个或加载倍数）存储或加载来自 多个通用寄存器中的多于一个存储器，此外，在多个寄存器指令在加载/存储单元中完成执行之前，调度单元调度浮点指令，其依赖于存储的源操作数据 在多个浮点寄存器的一个或多个浮点寄存器中，提供给浮点执行单元，其中调度浮点指令在多寄存器指令完成执行之前完成执行。

公开(公告)号：US5812823A

公开(公告)日：1998-09-22

申请号：US581794

申请日：1996-01-02

申请人： James Allan Kahle ,  Soummya Mallick ,  Arturo Martin-de-Nicolas

发明人： James Allan Kahle ,  Soummya Mallick ,  Arturo Martin-de-Nicolas

IPC分类号： G06F9/30 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F9/3879 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30174 ,  G06F9/45533 ,  G06F9/461

摘要： A system and method for performing an emulation context switch save and restore in a processor that executes host applications and emulates guest applications. The processor includes an operating system and a first register that is saved and restored by the operating system during a host application context switch. The method and system comprises renaming the special-purpose register to the first register when emulating guest applications. When an emulation context switch occurs, a context save and restore of the special-purpose register is performed through the first register without operating system modification.

摘要翻译： 用于执行仿真上下文切换的系统和方法在执行主机应用并且模拟来宾应用的处理器中保存和恢复。 处理器包括操作系统和在主机应用程序上下文切换期间由操作系统保存和恢复的第一寄存器。 该方法和系统包括在模拟客户应用程序时将专用寄存器重命名为第一寄存器。 当发生仿真上下文切换时，通过第一个寄存器执行专用寄存器的上下文保存和恢复，无需操作系统修改。

公开(公告)号：US5995743A

公开(公告)日：1999-11-30

申请号：US935007

申请日：1997-09-22

申请人： James Allan Kahle ,  Soummya Mallick

发明人： James Allan Kahle ,  Soummya Mallick

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48 ,  G06F9/44

CPC分类号： G06F9/4812 ,  G06F9/30174 ,  G06F9/3861 ,  G06F9/45554

摘要： A processor and method of interrupt handling in a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, in response to occurrence of an interrupt during emulation of a current guest instruction, an indication of a location in memory of the current guest instruction, an indication of a location in memory of a next guest instruction to be emulated, and an indication of a particular native instruction are stored. After an interrupt handler is executed, emulation is resumed by executing native instructions beginning with the particular native instruction. In response to execution of a native instruction of a first type before execution of a native instruction of a second type, the current guest instruction is fetched from memory. In response to execution of a native instruction of the second type before execution of a native instruction of the first type, the next guest instruction is fetched from memory without fetching the current guest instruction.

摘要翻译： 描述了处理器中的处理器和方法，该处理器具有本地指令集并且模拟客户指令集中的访客指令。 根据该方法，响应于在当前客户指令的仿真期间发生中断，当前客户指令的存储器中的位置的指示，要被仿真的下一个客户指令的存储器中的位置的指示，以及 存储特定本机指令的指示。 执行中断处理程序后，通过以特定的本机指令开始执行本地指令来恢复仿真。 响应于在执行第二类型的本机指令之前执行第一类型的本机指令，从存储器中取出当前的客户指令。 响应于在执行第一类型的本机指令之前执行第二类型的本地指令，从存储器中取出下一个访客指令而不取得当前的客户指令。

公开(公告)号：US5870575A

公开(公告)日：1999-02-09

申请号：US934644

申请日：1997-09-22

申请人： James Allan Kahle ,  Soummya Mallick

发明人： James Allan Kahle ,  Soummya Mallick

IPC分类号： G06F9/455

CPC分类号： G06F9/45504

摘要： A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of guest instructions including at least one unconditional indirect guest branch instruction is stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt. The entry includes an indication of a location in memory of at least one semantic routine. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines. The semantic routine utilized to emulate a first type of unconditional indirect guest branch instruction calculates a speculative return address, temporarily stores the speculative return address in memory, and initiates fetching at a target address. The semantic routine utilized to emulate a second type of unconditional indirect guest branch instruction retrieves the speculative return address from memory, initiates fetching of guest instructions at the speculative return address, and thereafter calculates a correct return address.

摘要翻译： 描述了一种处理器和操作处理器的方法，该处理器具有本地指令集并且在来宾指令集内仿真访客指令。 根据该方法，包括至少一条无条件间接访客分支指令的一系列访客指令被存储在存储器中。 此外，由本地指令形成并且可以用于模拟一系列访客指令的一个或多个语义例程被存储在存储器中。 对于一系列访客指令中的每个访客指令，条目按收据顺序存储在多个入口队列中。 该条目包括记忆至少一个语义例程的位置的指示。 响应于多入口队列中的条目，通过使用条目访问和执行一个或多个语义例程中的选定的条目来在处理器中仿真一系列访客指令。 用于模拟第一类型的无条件间接访客分支指令的语义程序计算推测返回地址，将推测返回地址临时存储在存储器中，并且在目标地址发起提取。 用于模拟第二种类型的无条件间接访客分支指令的语义程序从存储器检索推测返回地址，发起在推测返回地址获取访客指令，然后计算正确的返回地址。

公开(公告)号：US5619408A

公开(公告)日：1997-04-08

申请号：US387145

申请日：1995-02-10

申请人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell A. Reininger

发明人： Bryan Black ,  Marvin A. Denman ,  Lee E. Eisen ,  Robert T. Golla ,  Albert J. Loper, Jr. ,  Soummya Mallick ,  Russell A. Reininger

IPC分类号： G06F9/30 ,  G06F9/318 ,  G05B15/00

CPC分类号： G06F9/3017 ,  G06F9/30145

摘要： A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.

摘要翻译： 公开了一种用于处理包括具有多个执行单元的处理器的数据处理系统内的指令的方法和系统。 根据本发明的方法，从存储器中检索存储在数据处理系统内的存储器内的多个指令。 解码指令数目中的选择指令，以确定所选择的指令是否由处理器执行时是无效的。 在本发明的优选实施例中，无效指令包括具有无效操作码的指令和不会改变处理器内的任何数据寄存器的值的指令。 响应于确定所选择的指令如果由处理器执行将是无效的，则在将所选择的指令分派到多个执行单元之一之前，所选择的指令被重新编码为指定的指令格式。 在调度之前检测无效指令可减少调度程序中所需的解码逻辑，并提高处理器的性能。

公开(公告)号：US5956495A

公开(公告)日：1999-09-21

申请号：US934857

申请日：1997-09-22

申请人： James Allan Kahle ,  Soummya Mallick

发明人： James Allan Kahle ,  Soummya Mallick

IPC分类号： G06F9/32 ,  G06F9/455

CPC分类号： G06F9/30174 ,  G06F9/3879 ,  G06F9/45504

摘要： A series of guest instructions including at least one guest branch instruction and other guest instructions are stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each other guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt of the other guest instructions. Each entry includes an indication of a location in memory of at least one semantic routine and a condition field indicating conditions that may be set or reset by the associated guest instruction. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines. In response to detection of a conditional guest branch instruction in the series of guest instructions, a determination is made whether an entry in the multiple-entry queue associated with an instruction preceding the conditional guest branch instruction in the series has a condition field including an indication of a condition upon which the conditional branch instruction depends. If so, the indication is utilized to resolve the conditional guest branch instruction.

摘要翻译： 包括至少一个客户分支指令和其他访客指令的一系列访客指令被存储在存储器中。 此外，由本地指令形成并且可以用于模拟一系列访客指令的一个或多个语义例程被存储在存储器中。 对于一系列访客指令中的每个其他客人指令，根据接收到其他访客指令的顺序，将条目存储在多个入口队列中。 每个条目包括存储至少一个语义例程的位置的指示和指示可以由相关联的客户指令设置或重置的条件的条件字段。 响应于多入口队列中的条目，通过使用条目访问和执行一个或多个语义例程中的选定的条目来在处理器中仿真一系列访客指令。 响应于一系列访客指令中的条件访客分支指令的检测，确定与该系列中的条件访客分支指令之前的指令相关联的多入口队列中的条目是否具有包括指示的条件字段 条件分支指令所依赖的条件。 如果是，则使用该指示来解析条件访客分支指令。