A protection circuit for a CMOS integrated circuit which is biased with a first voltage and a second voltage includes a voltage divider, a voltage comparator, and a switch. The full level of the first voltage is higher than that of the second voltage. The voltage divider divides the first voltage to be compared with the second voltage in the voltage comparator. The switch is controlled by the voltage comparator. The switch isolates the CMOS integrated circuit from the first voltage when the first voltage is lower than the second voltage. Therefore, no forward bias current path exists in the CMOS integrated circuit even though the voltage levels of the first and second voltages reach their full levels at different times.