公开(公告)号：US5760631A

公开(公告)日：1998-06-02

申请号：US685309

申请日：1996-07-23

申请人： Ta-Lee Yu ,  Ling-Yen Yeh

发明人： Ta-Lee Yu ,  Ling-Yen Yeh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0948 ,  G05F1/20

CPC分类号： H01L27/0251 ,  H01L27/0218 ,  H03K19/00315

摘要： A protection circuit for a CMOS integrated circuit which is biased with a first voltage and a second voltage includes a voltage divider, a voltage comparator, and a switch. The full level of the first voltage is higher than that of the second voltage. The voltage divider divides the first voltage to be compared with the second voltage in the voltage comparator. The switch is controlled by the voltage comparator. The switch isolates the CMOS integrated circuit from the first voltage when the first voltage is lower than the second voltage. Therefore, no forward bias current path exists in the CMOS integrated circuit even though the voltage levels of the first and second voltages reach their full levels at different times.

摘要翻译： 用于以第一电压和第二电压偏置的CMOS集成电路的保护电路包括分压器，电压比较器和开关。 第一电压的全部电平高于第二电压。 分压器将电压比较器中的第一电压与第二电压进行比较。 开关由电压比较器控制。 当第一电压低于第二电压时，开关将CMOS集成电路与第一电压隔离。 因此，即使第一和第二电压的电压电平在不同时间达到满量程，CMOS集成电路中也不存在正向偏置电流路径。

公开(公告)号：US5889309A

公开(公告)日：1999-03-30

申请号：US770650

申请日：1996-12-19

申请人： Ta-Lee Yu ,  Chau-Neng Wu ,  Ling-Yen Yeh ,  Frank S-T Lin ,  Konrad Young

发明人： Ta-Lee Yu ,  Chau-Neng Wu ,  Ling-Yen Yeh ,  Frank S-T Lin ,  Konrad Young

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L23/62

CPC分类号： H01L27/0259 ,  H01L27/0658

摘要： An electrostatic discharge protection circuit formed in a semiconductor substrate includes a vertical bipolar junction transistor having a base which is grounded, an emitter connected to an output/input bonding pad of an integrated circuit, and a collector connected to a high power source via a resistor. The resistor is a parasitic resistor created by controlling the distance between the diffusion regions or the distance between a p-type well region and an n-type well region or formed by a lightly doped diffusion region in the semiconductor substrate to prevent current crowding and increase electrostatic protection.

摘要翻译： 形成在半导体衬底中的静电放电保护电路包括：具有接地的基极的垂直双极结型晶体管，连接到集成电路的输出/输入接合焊盘的发射极和经由电阻器连接到高功率源的集电极 。 电阻器是通过控制扩散区域之间的距离或p型阱区域和n型阱区域之间的距离或由半导体衬底中的轻掺杂扩散区域形成的寄生电阻器，以防止电流拥挤并增加 静电保护。

公开(公告)号：US20070268046A1

公开(公告)日：2007-11-22

申请号：US11754957

申请日：2007-05-29

申请人： Ta-Lee Yu ,  Lei Wang ,  Li Da

发明人： Ta-Lee Yu ,  Lei Wang ,  Li Da

IPC分类号： H03K3/00

CPC分类号： H03K19/003

摘要： A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

摘要翻译： 一种用于控制输入/输出驱动器的系统和方法。 该系统包括被配置为接收第一电源电压和第二电源电压并产生控制信号的控制系统，以及包括第一门，第一终端和第二终端的第一晶体管。 第一栅极被配置为接收控制信号，并且第一端子被配置为接收第一电源电压。 另外，该系统包括包括第二栅极，第三端子和第四端子的第二晶体管，并且第二栅极耦合到第二端子。 此外，该系统包括包括第三栅极，第五端子和第六端子的第三晶体管，并且第三栅极被配置为接收控制信号。 此外，该系统包括耦合到第四端子和第五端子的输入/输出焊盘。

公开(公告)号：US06872987B2

公开(公告)日：2005-03-29

申请号：US10462287

申请日：2003-06-16

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L21/332 ,  H01L27/02 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7436 ,  H01L27/0259 ,  H01L29/66121 ,  H01L29/66393 ,  H01L29/87

摘要： A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

摘要翻译： 对于与浅沟槽隔离结构一起使用的SCR ESD保护器件，描述了一种新颖的器件结构和工艺。 本发明结合了跨越SCR二极管结元件的多晶硅栅极以及SCR元件和相邻STI结构之间的桥接。 有战略地定位的多晶硅栅极的存在有效地抵消了非平面STI“下拉”区域的有害影响，以及补偿硅化物结构与由STI元件限制的二极管元件的有效结深度的相互作用。 将栅极连接到适当的电压源，例如通常接地的SCR阳极输入电压和SCR阴极电压，可以降低ESD保护器件的正常工作泄漏。

公开(公告)号：US06555458B1

公开(公告)日：2003-04-29

申请号：US10046802

申请日：2002-01-14

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an electrical metal fuse for use with a semiconductor integrated circuit device. At least two varying trench metal depths may be formed on a substrate to configure the electrical metal fuse thereon. Additionally, at least two different widths of single metal lines, may be configured on the substrate. As a result of the two different trench depths and two different widths of metal formed thereon to create the electrical metal fuse, increases in current density gradients and thermal gradients thereof can be generated. The trench metal depths and width of metal are formed from copper. The electrical metal fuse generally comprises a current density ratio greater than 10 to 1.

摘要翻译： 一种用于形成用于半导体集成电路器件的电金属熔丝的方法。 可以在衬底上形成至少两个变化的沟槽金属深度以在其上配置电金属熔丝。 另外，可以在衬底上配置至少两个不同宽度的单个金属线。 由于两个不同的沟槽深度和两个不同宽度的金属形成在其上以产生电金属熔断器，所以可以产生电流密度梯度和其热梯度的增加。 金属的沟槽金属深度和宽度由铜形成。 电气金属保险丝通常包括大于10比1的电流密度比。

公开(公告)号：US06353237B1

公开(公告)日：2002-03-05

申请号：US09365431

申请日：1999-08-02

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L2974

CPC分类号： H01L27/0262 ,  H01L27/0255

摘要： The present invention provides an ESD protection circuit having at least one semiconductor-controlled rectifier and a diode. The SCR having a floating anode gate is connected between a first circuit node a second circuit node. The diode is connected between an anode and a cathode gate of the SCR to activate the SCR so that a potential between the first circuit node and second circuit node can be clamped at about a holding voltage of the SCR during an ESD event.

摘要翻译： 本发明提供一种具有至少一个半导体可控整流器和二极管的ESD保护电路。 具有浮动阳极栅极的SCR连接在第一电路节点和第二电路节点之间。 二极管连接在SCR的阳极和阴极栅之间，以激活SCR，使得在ESD事件期间，第一电路节点和第二电路节点之间的电位可以在SCR的约保持电压处被钳位。

公开(公告)号：US06329223B2

公开(公告)日：2001-12-11

申请号：US09784145

申请日：2001-02-16

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L23/60 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/45099 ,  H01L2924/00

摘要： An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

摘要翻译： 集成电路封装包括半导体芯片，多个有线引脚和至少一个非有线引脚。 无线引脚的尺寸被最小化，或者无线引脚被消除，以便增加引脚间距。 引脚间距的增加防止了由于非接线引脚的静电应力引起的集成电路封装中的静电放电故障。

公开(公告)号：US06297536B2

公开(公告)日：2001-10-02

申请号：US09270830

申请日：1999-03-18

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L3300

CPC分类号： H01L27/0814 ,  H01L27/0255 ,  H01L29/8611

摘要： A diode structure compatible with silicide processes for electrostatic discharge protection is disclosed. The diode structure comprises a semiconductor layer of a first conductivity type, a diffusion region of a second conductivity type formed in the semiconductor layer, and a doped region of the second conductivity type formed in the semiconductor layer around the diffusion region. The doped region has a doping concentration less than that of the diffusion region to provide a ballastic resistance under a high current stressing condition.

摘要翻译： 公开了一种与用于静电放电保护的硅化物工艺兼容的二极管结构。 二极管结构包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的扩散区和形成在扩散区周围的半导体层中的第二导电类型的掺杂区。 掺杂区域的掺杂浓度小于扩散区域的掺杂浓度，以在高电流应力条件下提供抗弹性电阻。

公开(公告)号：US06274910B1

公开(公告)日：2001-08-14

申请号：US09457922

申请日：1999-12-09

申请人： Ta-Lee Yu

发明人： Ta-Lee Yu

IPC分类号： H01L2972

CPC分类号： H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit is fabricated on a semiconductor block on an insulating layer overlying a supporting substrate. The ESD protection circuit comprises a first N-type doped region, a first P-type doped region, a second N-type doped region and a second P-type doped region sequentially formed in the semiconductor block, and a stacked structure overlying the first P-type doped region and the second N-type doped region, wherein the first N-type doped region is more heavily doped than the second N-type doped region and the first P-type doped region is more lightly doped than the second P-type doped region.

摘要翻译： 在覆盖在支撑基板上的绝缘层上的半导体块上制造ESD保护电路。 ESD保护电路包括依次形成在半导体块中的第一N型掺杂区，第一P型掺杂区，第二N型掺杂区和第二P型掺杂区，以及叠置在第一 P型掺杂区域和第二N型掺杂区域，其中第一N型掺杂区域比第二N型掺杂区域更重掺杂，并且第一P型掺杂区域比第二P型掺杂区域更加轻掺杂 型掺杂区域。

公开(公告)号：US6157070A

公开(公告)日：2000-12-05

申请号：US27533

申请日：1998-02-23

申请人： Shi-Tron Lin ,  Ta-Lee Yu

发明人： Shi-Tron Lin ,  Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L29/76 ,  H01L27/10 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0921 ,  H01L27/0266

摘要： In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.

摘要翻译： 在多电源CMOS IC中，如果在上电期间VDDH施加得比VDDL慢，则通常反向偏置的一些扩散结可能会瞬间变为正向偏置，并产生闭锁以产生对电路的永久性损坏。 因此，提供了防止在多电源IC中闭锁的保护电路。 保护电路包括一个N沟道MOSFET，其栅极连接到高电压总线，其漏极连接到低压电源，其源极连接到低压母线以控制上电顺序 高电压和低电压的多电源IC，并防止闩锁。 N沟道MOSFET可以具有不同的模式，例如具有低阈值电压的增强模式，耗尽模式或增强模式。