发明授权
- 专利标题: Cache memory in a data processing system
- 专利标题(中): 数据处理系统中的高速缓存
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申请号: US629927申请日: 1996-04-12
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公开(公告)号: US5765190A公开(公告)日: 1998-06-09
- 发明人: Joseph C. Circello , Anup S. Tirumala , Vasudev J. Bibikar
- 申请人: Joseph C. Circello , Anup S. Tirumala , Vasudev J. Bibikar
- 申请人地址: IL Schaumburg
- 专利权人: Motorola Inc.
- 当前专利权人: Motorola Inc.
- 当前专利权人地址: IL Schaumburg
- 主分类号: G06F12/08
- IPC分类号: G06F12/08 ; G06F12/12 ; G06F12/00
摘要:
A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15) If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
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