- 专利标题: Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories
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申请号: US518414申请日: 1995-08-24
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公开(公告)号: US5783949A公开(公告)日: 1998-07-21
- 发明人: William Robert Reohr , Yuen Hung Chan , Pong-Fei Lu
- 申请人: William Robert Reohr , Yuen Hung Chan , Pong-Fei Lu
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C7/06 ; G11C8/10 ; G11C11/419 ; H01L21/822 ; H01L27/04 ; H01L27/10 ; H03F3/45 ; H03K19/003 ; H03R19/0944
摘要:
A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.
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