A circuit for performing either single precision or double precision arithmetic operations on data, a system including such a circuit, and a method implemented by the system. Preferably, the circuit is an arithmetic manipulation unit (AMU) which performs arithmetic operations on N-bit words in a single precision mode and on 2N-bit words in a double precision mode. The AMU concatenates two N-bit words in the double precision mode thus producing a 2N-bit operand, and performs a selected one of several arithmetic operations on the operand and a second 2N-bit operand. Preferably, the AMU performs a double precision operation in two cycles: a first cycle generating a first operand and loading the operand to an output register; and a second cycle in which a second operand is generated from a second pair of N-bit parts from the memory, the first operand is fed back from the output register, and an arithmetic operation is performed on the two operands. The system preferably includes a multi-port memory, executes instructions in pipelined fashion, and operates in a single precision mode to fetch two N-bit operands from the memory in a single pipeline cycle using two address pointers and in a double precision mode to fetch two N-bit words from the memory in a single cycle. In a double precision mode, the system can fetch two N-bit parts stored in consecutive memory locations in a single cycle, by generating and asserting to the memory two addresses in response to one address pointer.