Invention Grant
US5790874A Information processing apparatus for reducing power consumption by
minimizing hamming distance between consecutive instruction
失效
用于通过使连续指令之间的汉明距离最小化来降低功耗的信息处理装置
- Patent Title: Information processing apparatus for reducing power consumption by minimizing hamming distance between consecutive instruction
- Patent Title (中): 用于通过使连续指令之间的汉明距离最小化来降低功耗的信息处理装置
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Application No.: US536180Application Date: 1995-09-29
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Publication No.: US5790874APublication Date: 1998-08-04
- Inventor: Hiroyuki Takano , Nobuhiro Ide , Takeshi Yoshida
- Applicant: Hiroyuki Takano , Nobuhiro Ide , Takeshi Yoshida
- Applicant Address: JPX Kawasaki
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JPX Kawasaki
- Priority: JPX6-237680 19940930; JPX6-261394 19940930
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F9/318 ; G06F9/38 ; G06F9/45
Abstract:
An instruction sequence optimization apparatus optimizes programs used in an information processing system that includes a program memory for storing programs, and a processing unit for fetching the programs from the program memory via an instruction bus. The apparatus includes an instruction sequence analyzing unit for analyzing mutual dependence relations between respective instructions constituting the program, and an instruction sequence modifying unit for modifying sequences of the instructions insofar as the mutual dependence relations analyzed by the instruction sequence analyzing unit are not influenced, to thus reduce Hamming distances between bit sequences appearing on the instruction bus when the instructions are transferred from the program memory to the processing unit.
Public/Granted literature
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