- 专利标题: Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output
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申请号: US755930申请日: 1996-11-25
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公开(公告)号: US5793686A公开(公告)日: 1998-08-11
- 发明人: Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
- 申请人: Kiyohiro Furutani , Tsukasa Ooishi , Mikio Asakura , Hideto Hidaka , Kei Hamade , Yoshito Nakaoka
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-308866 19951128
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C7/10 ; G11C11/401 ; G11C29/00 ; G11C29/14 ; G11C29/34 ; G11C29/38 ; G11C7/00
摘要:
Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.
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