- 专利标题： Delay locked loop implementation in a synchronous dynamic random access memory
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申请号： US319042申请日： 1994-10-06
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公开(公告)号： US5796673A公开(公告)日： 1998-08-18
- 发明人: Richard C. Foss , Peter B. Gillingham , Graham Allan
- 申请人： Richard C. Foss , Peter B. Gillingham , Graham Allan
- 申请人地址： CAX Kanata
- 专利权人： Mosaid Technologies Incorporated
- 当前专利权人： Mosaid Technologies Incorporated
- 当前专利权人地址： CAX Kanata
- 主分类号： G11C7/10
- IPC分类号： G11C7/10 ; G11C7/22 ; H03D3/24 ; H03K5/13 ; H03L7/081 ; G11C8/00
摘要：
A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
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