公开(公告)号：US08369182B2

公开(公告)日：2013-02-05

申请号：US12547955

申请日：2009-08-26

申请人： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

发明人： Richard C. Foss ,  Peter B. Gillingham ,  Graham Allan

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814

摘要： A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

摘要翻译： 用于同步存储器的时钟施加电路包括用于接收时钟输入信号的时钟输入，连接到用于接收驱动时钟信号的同步存储器的装置和用于接收用于传送时钟驱动的时钟输入信号的抽头延迟线 与时钟输入信号同步但延迟到同步存储器，延迟是时钟输入信号的时钟周期的一小部分。

公开(公告)号：US20130003478A1

公开(公告)日：2013-01-03

申请号：US13490700

申请日：2012-06-07

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C7/06

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors.

摘要翻译： 具有位线对的动态随机存取存储器（DRAM），每对都连接到第一位线读出放大器，与形成阵列的位线对交叉的字线，连接到位线的电荷存储单元，每个具有连接到位线的使能输入 字线，位线读出放大器以二维阵列连接，成对的初级数据总线通过第一存取晶体管连接到阵列的每一行中的多个相应的位线读出放大器，用于使第一存取晶体管的列，数据总线 每个连接到对应的数据总线对的读出放大器，辅助数据总线，通过第二存取晶体管连接到数据总线读出放大器的次级数据总线，以及用于使能第二存取晶体管的装置。

公开(公告)号：US20090073792A1

公开(公告)日：2009-03-19

申请号：US12221195

申请日：2008-07-31

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C7/06

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

公开(公告)号：US07486580B2

公开(公告)日：2009-02-03

申请号：US11476422

申请日：2006-06-28

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C7/02

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

公开(公告)号：USRE40552E1

公开(公告)日：2008-10-28

申请号：US10032431

申请日：2001-12-21

申请人： Richard C. Foss ,  Peter B. Gillingham ,  Robert Harland ,  Masami Mitsuhashi ,  Atsushi Wada

发明人： Richard C. Foss ,  Peter B. Gillingham ,  Robert Harland ,  Masami Mitsuhashi ,  Atsushi Wada

IPC分类号： G11C7/00

CPC分类号： G11C7/00

摘要： Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plurality of bit storage capacitors, a folded bit line for receiving charge stored on one of the capacitors, having bit line capacitance, a sense amplifier having a pair of sense nodes for sensing a voltage differential across the sense nodes, apparatus connected to the bit line and the sense nodes for imperfectly isolating the sense nodes from the bit line whereby current can leak therethrough, apparatus for enabling the sense amplifier and for disabling the isolating apparatus and thereby removing the isolation between the sense amplifier and the bit line, whereby current passing through the sense amplifier to the sense nodes is enabled to charge the bit line capacitance through the isolating apparatus to predetermined logic voltage level.

摘要翻译： 用于控制位线感测的装置和方法，其有助于随时分布的位线充电电流的分布，并且有助于将感测模式快速升高到完全逻辑电平。 一个实施例包括多个位存储电容器，用于接收存储在其中一个电容器上的电荷的折叠位线，具有位线电容，读出放大器具有用于感测跨感测节点的电压差的一对感测节点， 连接到位线的装置和感测节点，用于使感测节点与位线不完全隔离，由此电流可以泄漏，用于使读出放大器和禁用隔离装置的装置，从而消除读出放大器和位之间的隔离 从而使通过感测放大器的电流到感测节点能够通过隔离装置将位线电容充电到预定的逻辑电压电平。

公开(公告)号：US06661723B2

公开(公告)日：2003-12-09

申请号：US10278195

申请日：2002-10-22

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C702

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

公开(公告)号：US06195282B1

公开(公告)日：2001-02-27

申请号：US08986358

申请日：1997-12-08

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C1124

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitline pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

摘要翻译： 具有位线对的动态随机存取存储器（DRAM），每对连接到第一位线读出放大器，与形成阵列的位线对交叉的字线，连接到位线的电荷存储单元，每个具有连接到位线的使能输入 字线，位线读出放大器以二维阵列连接，成对的初级数据总线通过第一存取晶体管连接到阵列的每一行中的多个相应的位线读出放大器，用于使第一存取晶体管的列，数据总线 读出放大器各自连接到对应的数据总线对，辅助数据总线，次级数据总线通过第二存取晶体管连接到数据总线读出放大器，以及用于使能第二存取晶体管的装置，由此每个主数据总线对可以被多个 阵列的相应行中的读出放大器和辅助数据总线可以由多个prim共享 ary数据总线对。

公开(公告)号：US5822333A

公开(公告)日：1998-10-13

申请号：US624213

申请日：1996-03-29

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C29/00 ,  G11C29/12 ,  G06F11/00

CPC分类号： G11C29/12 ,  G11C29/003

摘要： A method of testing a digital memory comprised of bit storage locations, comprising writing a bit to a first bit storage location, then driving the stored bit sequentially through a plurality of the bit storage locations, reading a last bit storage location of the plurality of bit storage locations, and testing a bit read from the last bit storage location.

摘要翻译： 一种测试包括位存储位置的数字存储器的方法，包括将位写入第一位存储位置，然后通过多个位存储位置顺序地驱动存储的位，读取多个位的最后位存储位置 存储位置，并测试从最后一位存储位置读取的位。

公开(公告)号：US20100128546A1

公开(公告)日：2010-05-27

申请号：US12562452

申请日：2009-09-18

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C7/00 ,  G11C7/02 ,  H03K19/177

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.

摘要翻译： 具有位线对的动态随机存取存储器（DRAM），每对都连接到第一位线读出放大器，与形成阵列的位线对交叉的字线，连接到位线的电荷存储单元，每个具有连接到位线的使能输入 字线，位线读出放大器以二维阵列连接，成对的初级数据总线通过第一存取晶体管连接到阵列的每一行中的多个相应的位线读出放大器，用于使第一存取晶体管的列，数据总线 读出放大器各自连接到对应的数据总线对，辅助数据总线，次级数据总线通过第二存取晶体管连接到数据总线读出放大器，以及用于使能第二存取晶体管的装置，由此每个主数据总线对可以被多个 阵列的相应行中的读出放大器和辅助数据总线可以由多个pri共享 玛丽数据总线对。

公开(公告)号：US07095666B2

公开(公告)日：2006-08-22

申请号：US10691111

申请日：2003-10-22

申请人： Richard C. Foss

发明人： Richard C. Foss

IPC分类号： G11C7/02

CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.